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參數(shù)資料
| 型號(hào)： | AD9548/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 112/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 設(shè)計(jì)資源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要屬性： | 62.5 ~ 450 MHz 輸出頻率 |
| 次要屬性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
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Data Sheet
AD9548
Rev. E | Page 99 of 112
Table 133. SYSCLK Status
Address
Bits
Bit Name
Description
0x0D01
[7:5]
Unused
[4]
Stable
The control logic sets this bit when the device considers the system clock to be
stable (see the System Clock Stability Timer section).
[3:2]
Unused
[1]
Cal in progress
The control logic holds this bit set while the system clock calibration is in progress.
[0]
Lock detected
Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked (or the PLL is disabled).
Register 0x 0D02 to Register 0x0D09—IRQ Monitor
If not masked via the IRQ mask register (Address 0x0209 to Address 0x0210), then the appropriate IRQ monitor bit is set to a Logic 1
when the indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0x0A04 to Address 0x0A0B), the
reset all IRQs bit (Register 0x0A03, Bit 1), or a device reset.
Table 134. IRQ Monitor for SYSCLK
Address
Bits
Bit Name
Description
0x0D02
[7:6]
Unused
[5]
SYSCLK unlocked
Indicates a SYSCLK PLL state transition from locked to unlocked
[4]
SYSCLK locked
Indicates a SYSCLK PLL state transition from unlocked to locked
[3:2]
Unused
[1]
SYSCLK Cal complete
Indicates that SYSCLK calibration has completed
[0]
SYSCLK Cal started
Indicates that SYSCLK calibration has begun
Table 135. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bits
Bit Name
Description
0x0D03
[7:4]
Unused
[3]
Distribution sync
Indicates a distribution sync event
[2]
Watchdog timer
Indicates expiration of the watchdog timer
[1]
EEPROM fault
Indicates a fault during an EEPROM load or save operation
[0]
EEPROM complete
Indicates successful completion of an EEPROM load or save operation
Table 136. IRQ Monitor for the Digital PLL
Address
Bits
Bit Name
Description
0x0D04
[7]
Switching
Indicates that the DPLL is switching to a new reference
[6]
Closed
Indicates that the DPLL has entered closed-loop operation
[5]
Freerun
Indicates that the DPLL has entered free-run mode
[4]
Holdover
Indicates that the DPLL has entered holdover mode
[3]
Freq unlocked
Indicates that the DPLL lost frequency lock
[2]
Freq locked
Indicates that the DPLL has acquired frequency lock
[1]
Phase unlocked
Indicates that the DPLL lost phase lock
[0]
Phase locked
Indicates that the DPLL has acquired phase lock
Table 137. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit
Address
Bits
Bit Name
Description
0x0D05
[7:5]
Unused
[4]
History updated
Indicates the occurrence of a tuning word history update
[3]
Freq unclamped
Indicates a frequency limiter state transition from clamped to unclamped
[2]
Freq clamped
Indicates a frequency limiter state transition from unclamped to clamped
[1]
Phase slew unlimited
Indicates a phase slew limiter state transition from slew limiting to not slew
limiting
[0]
Phase slew limited
Indicates a phase slew limiter state transition from not slew limiting to slew
limiting
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