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參數(shù)資料
| 型號： | AD9518-4ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
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Data Sheet
AD9518-4
Rev. B | Page 59 of 64
APPLICATIONS INFORMATION
Considering an ideal ADC of infinite resolution where the step
size and quantization error can be ignored, the available SNR
can be expressed approximately by
FREQUENCY PLANNING USING THE AD9518
The AD9518 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9518, keep in mind the following
guidelines.
π
×
=
J
At
f
dB
SNR
2
1
log
20
)
(
The AD9518 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 52 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
fA (MHz)
S
NR
(
d
B)
EN
O
B
10
1k
100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
t
J
= 100f
s
200fs
400fs
1ps
2ps
10ps
SNR = 20log
1
2πfAtJ
06
43
3-
04
4
Within the AD9518 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9518 family. If the desired
frequency plan can be achieved with a version of the AD9518
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter.
However, choosing a higher VCO frequency may result in more
flexibility in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
Figure 52. SNR and ENOB vs. Analog Input Frequency
For more information, see the AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter; and the
AN-501 Application Note, Aperture Uncertainty and ADC System
Performance, at www.analog.com.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9518 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can provide
superior clock performance in a noisy environment.) The AD9518
features LVPECL outputs that provide differential clock outputs,
which enable clock solutions that maximize converter SNR
performance. The input requirements of the ADC (differential
or single-ended, logic level, termination) should be considered
when selecting the best clocking/converter solution.
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9518-4ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 1.8GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9518-4A-PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9518-4BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9520 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers |
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