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參數(shù)資料
| 型號： | AD9518-4ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
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Data Sheet
AD9518-4
Rev. B | Page 33 of 64
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
NCE
HOLD
0
1
0
1
DIVIDE BY
2, 3, 4, 5, OR 6
06
43
3-
0
70
Figure 39. Reference and VCO Status Monitors
VCO Calibration
The AD9518 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. VCO calibration centers
the dc voltage at the internal VCO input (at the LF pin) for the
selected configuration; this is normally required only during
initial configuration and any time the PLL settings change. VCO
calibration is controlled by a calibration controller driven by the
R divider output. The calibration requires that the input reference
clock be present at the REFIN pins, and that the PLL be set up
properly to lock the PLL loop. During the first initialization after
a power-up or a reset of the AD9518, a VCO calibration sequence
is initiated by setting Register 0x018[0] = 1b. This can be done
during initial setup, before executing an update registers operation
(Register 0x232[0] = 1b). Subsequent to initial setup, a VCO
calibration sequence is initiated by resetting Register 0x018[0] = 0b,
executing an update registers operation, setting Register 0x018[0] =
1b, and executing another update registers operation. A readback
bit (Bit 6 in Register 0x1F) indicates when a VCO calibration is
finished by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is as follows:
1.
Program the PLL registers to the proper values for the PLL
loop. Note that that automatic holdover mode must be
disabled, and the VCO divider must not be set to “Static.”
2.
Ensure that the input reference signal is present.
3.
For the initial setting of the registers after a power-up or reset,
initiate VCO calibration by setting Register 0x018[0] = 1b.
Subsequently, whenever a calibration is desired, set
Register 0x018[0] = 0b, update registers; and then set
Register 0x018[0] = 1b, update registers.
4.
A sync operation is initiated internally, causing the outputs
to go to a static state determined by normal sync function
operation.
5.
The VCO calibrates to the desired setting for the requested
VCO frequency.
6.
Internally, the SYNC signal is released, allowing outputs
to continue clocking.
7.
The PLL loop is closed.
8.
The PLL locks.
A SYNC is executed during the VCO calibration; therefore, the
outputs of the AD9518 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 44
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9518-4ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 1.8GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9518-4A-PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9518-4BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9520 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers |
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