參數(shù)資料
型號： AD9516-5BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 52/76頁
文件大小： 0K
描述： IC CLOCK GEN W/PLL 64-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9516-5
Rev. A | Page 56 of 76
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01A
6
Reference
frequency
monitor
threshold
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the CLK
frequency monitor’s detection threshold (see Table 12: REF1, REF2, and CLK frequency status monitor parameter).
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
[5:0]
LD pin control
Selects the LD pin signal.
5
4
3
2
1
0
Level or
Dynamic
Signal
Signal at LD Pin
0
LVL
Digital lock detect (high = lock, low = unlock) (default)
0
1
DYN
P-channel, open-drain lock detect (analog lock detect)
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect)
0
1
HIZ
High-Z LD pin
0
1
0
CUR
Current source lock detect (110 μA when DLD is true)
0
X
LVL
Ground (dc); for all other cases of 0x0XXXX not specified
The selections that follow are the same as for REFMON:
1
0
LVL
Ground (dc)
1
0
1
DYN
REF1 clock (differential reference when in differential mode)
1
0
1
0
DYN
REF2 clock (not available in differential mode)
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode)
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high
1
0
1
LVL
Status of REF1 frequency (active high)
1
0
1
0
LVL
Status of REF2 frequency (active high)
1
0
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
0
1
0
1
LVL
Status of CLK frequency (active high)
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2)
1
0
1
0
1
LVL
Digital lock detect (DLD); active high
1
0
1
0
LVL
Holdover active (active high)
1
0
1
LVL
Not available; do not use
1
0
LVL
VS (PLL supply)
1
0
1
DYN
REF1 clock (differential reference when in differential mode)
1
0
1
0
DYN
REF2 clock (not available in differential mode)
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode)
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low
1
0
1
LVL
Status of REF1 frequency (active low)
1
0
LVL
Status of REF2 frequency (active low)
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
0
1
LVL
Status of CLK frequency (active low)
1
0
LVL
Selected reference (low = REF2, high = REF1)
1
0
1
LVL
Digital lock detect (DLD); active low
1
0
LVL
Holdover active (active low)
1
LVL
Not available; do not use
0x01B
7
CLK frequency
monitor
Enables or disables CLK frequency monitor.
0: disables CLK frequency monitor (default).
1: enables CLK frequency monitor.
6
REF2 (REFIN)
frequency
monitor
Enables or disables REF2 frequency monitor.
0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
5
REF1 (REFIN)
frequency
monitor
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected
by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
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