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參數(shù)資料
| 型號： | AD9516-5BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN W/PLL 64-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9516-5
Rev. A | Page 36 of 76
A phase offset or delay in increments of the input clock cycle is
selectable. The channel dividers operate with a signal at their
inputs up to 1600 MHz. The features and settings of the dividers
are selected by programming the appropriate setup and control
VCO Divider
The VCO divider provides frequency division between the
external CLK input and the clock distribution channel dividers.
The VCO divider can be set to divide by 2, 3, 4, 5, or 6 (see
Table 55, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving six
LVPECL outputs (OUT0 to OUT5). Table 29 lists the register
locations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting
of the DCCOFF bits.
Divider
Low Cycles
M
High Cycles
N
Bypass
DCCOFF
0
0x190[7:4]
0x190[3:0]
0x191[7]
0x192[0]
1
0x193[7:4]
0x193[3:0]
0x194[7]
0x195[0]
2
0x196[7:4]
0x196[3:0]
0x197[7]
0x198[0]
1 Note that the value stored in the register = # of cycles minus 1. For example,
0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.
Channel Frequency Division (0, 1, and 2)
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, DX = 1.
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 2 to 32.
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
What are the M and N values for the channel?
Is the DCC enabled?
Is the VCO divider used?
What is the CLK input duty cycle?
The DCC function is enabled, by default, for each channel divider.
However, the DCC function can be disabled individually for each
channel divider by setting the DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
An even division must be set as M = N
An odd division must be set as M = N + 1
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as a percentage (%).
dividers for various configurations.
Table 30. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
DX
Output Duty Cycle
VCO
Divider
N + M + 2
DCCOFF = 1
DCCOFF = 0
Even
1 (divider
bypassed)
50%
Odd = 3
1 (divider
bypassed)
33.3%
50%
Odd = 5
1 (divider
bypassed)
40%
50%
Even,
Odd
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Even,
Odd
(N + 1)/
(N + M + 2)
50%, requires M = N + 1
Table 31. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
DX
Output Duty Cycle
VCO
Divider
N + M + 2
DCCOFF = 1
DCCOFF = 0
Even
1 (divider
bypassed)
50%
Odd = 3
1 (divider
bypassed)
33.3%
(1 + X%)/3
Odd = 5
1 (divider
bypassed)
40%
(2 + X%)/5
Even
(N + 1)/
(N + M + 2)
50%,
requires M = N
Odd
(N + 1)/
(N + M + 2)
50%,
requires M = N + 1
Odd = 3
Even
(N + 1)/
(N + M + 2)
50%,
requires M = N
Odd = 3
Odd
(N + 1)/
(N + M + 2)
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
Odd = 5
Even
(N + 1)/
(N + M + 2)
50%,
requires M = N
Odd = 5
Odd
(N + 1)/
(N + M + 2)
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
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| AD9516-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN W/PLL 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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