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參數資料
| 型號： | AD9516-5BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 24/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN W/PLL 64-LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9516-5
Rev. A | Page 30 of 76
Automatic revertive switchover relies on the REFMON pin to
indicate when REF1 disappears. By programming Register 0x01B =
0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed
to be high when REF1 is invalid, which commands the switch to
REF2. When REF1 is valid again, the REFMON pin goes low, and
the part again locks to REF1. The STATUS pin can also be used
for this function, and REF2 can be used as the preferred reference.
A switchover deglitch feature ensures that the PLL does not receive
rising edges that are far out of alignment with the newly selected
reference. Automatic nonrevertive switching is not supported.
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16,383 by
writing to Register 0x011 and Register 0x012. (Both R = 0 and
R = 1 give divide-by-1.) The output of the R divider goes to one
of the PFD inputs to be compared with the VCO frequency divided
by the N divider. The frequency applied to the PFD must not
exceed the maximum allowable frequency, which depends on
the antibacklash pulse setting (see Table 2).
The R counter has its own reset. The R counter can be reset via
the shared reset bit of the R, A, and B counters. It can also be
reset by a SYNC operation.
VCXO/VCO Feedback Divider N—P, A, B
The N divider is a combination of a prescaler (P) and two
counters, A and B. The total divider value is
N = (P × B) + A
where P can be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9516 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3, 4
and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 49, Register 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
When operating the AD9516 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in FD Mode 1,
FD Mode 2, or FD Mode 3, the A counter is not used (A = 0)
and the equation simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
in which case, the previous equation also applies.
By using combinations of DM and FD modes, the AD9516
can achieve values of N all the way down to N = 1 and up to N =
26,2175. Table 24 shows how a 10 MHz reference input can be
locked to any integer multiple of N.
Table 24. Using a 10 MHz Reference to Generate Different VCO Frequencies
fREF (MHz)
R
P
A
B
N
fVCO (MHz)
Mode
Conditions/Comments
10
1
1
10
FD
P = 1, B = 1 (A and B counters are bypassed).
10
1
2
1
2
20
FD
P = 2, B = 1 (A and B counters are bypassed).
10
1
3
30
FD
A counter is bypassed.
10
1
4
40
FD
A counter is bypassed.
10
1
5
50
FD
A counter is bypassed.
10
1
2
3
6
60
FD
A counter is bypassed.
10
1
2
0
3
6
60
DM
10
1
2
1
3
7
70
DM
Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.
If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz
to 300 MHz, use P = 1, and N = 7 or 11, respectively.
10
1
2
3
8
80
DM
10
1
2
1
4
9
90
DM
10
1
8
6
18
150
1500
DM
10
1
8
7
18
151
1510
DM
10
1
16
7
9
151
1510
DM
10
32
6
47
1510
DM
10
1
8
0
25
200
2000
DM
10
1
16
14
16
270
2700
DM
P = 8 is not allowed (2700 ÷ 8 > 300 MHz).
P = 32 is not allowed (A > B not allowed).
10
32
22
84
2710
DM
P = 32, A = 22, B = 84.
P = 16 is also permitted.
1 X = don’t care.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9516-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN W/PLL 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9516-5PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator |
| AD9517-0A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-0A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9517-0ABCPZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9517-0ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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