參數(shù)資料
型號(hào): AD9516-2/PCBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 9/80頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9516-2 2.2GHZ
產(chǎn)品培訓(xùn)模塊: Active Filter Design Tools
設(shè)計(jì)資源: AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-2 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9516-2
主要屬性: 2 輸入,14 輸出,2.2GHz VCO
次要屬性: CMOS、LVDS、LVPECL 輸出邏輯,ADIsimCLK&trade 圖形用戶界面
已供物品: 板,線纜,CD,電源
產(chǎn)品目錄頁(yè)面: 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD9516-2BCPZ-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
AD9516-2BCPZ-REEL7-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
Data Sheet
AD9516-2
Rev. C | Page 17 of 80
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CS
NC
S
DO
S
DI
O
R
ESET
PD
OU
T4
OU
T4
VS_
L
VPEC
L
OU
T5
OU
T5
VS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RE
F
IN
(
RE
F
1)
RE
F
IN
(
RE
F
2)
C
PR
SET
VS
G
ND
R
SET
VS
OU
T0
OU
T0
VS_
L
VPEC
L
OU
T1
OU
T1
VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
CLK
NC
SCLK
NC = NO CONNECT
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
GND
OUT2
VS_LVPECL
OUT3
VS
GND
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9516-2
TOP VIEW
(Not to Scale)
LVPECL LVPECL
L
VPEC
L
VPEC
L
V
DS
/CM
O
S
w
/F
INE
DE
L
AY
ADJ
US
T
L
V
DS
/CM
O
S
w
/F
INE
DE
L
AY
ADJ
US
T
06421-
003
NOTES
1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
1, 11, 12, 30,
31, 32, 38,
49, 50, 51,
57, 60, 61
I
Power
VS
3.3 V Power Pins.
2
I
3.3 V CMOS
REFMON
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
3
O
3.3 V CMOS
LD
Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x1A.
4
I
Power
VCP
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V.
5
O
3.3 V CMOS
CP
Charge Pump (Output). Connects to external loop filter.
6
O
3.3 V CMOS
STATUS
Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.
7
I
3.3 V CMOS
REF_SEL
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 k
pull-down resistor.
8
I
3.3 V CMOS
SYNC
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 k pull-up resistor.
9
I
Loop filter
LF
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large (>500 kHz) loop bandwidths.
10
O
Loop filter
BYPASS
This pin is for bypassing the LDO to ground with a capacitor.
13
I
Differential
clock input
CLK
Along with CLK, this is the differential input for the clock distribution section.
14
I
Differential
clock input
CLK
Along with CLK, this is the differential input for the clock distribution section.
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