參數資料
型號: AD9516-2/PCBZ
廠商: Analog Devices Inc
文件頁數: 58/80頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9516-2 2.2GHZ
產品培訓模塊: Active Filter Design Tools
設計資源: AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-2 BOM
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9516-2
主要屬性: 2 輸入,14 輸出,2.2GHz VCO
次要屬性: CMOS、LVDS、LVPECL 輸出邏輯,ADIsimCLK&trade 圖形用戶界面
已供物品: 板,線纜,CD,電源
產品目錄頁面: 776 (CN2011-ZH PDF)
相關產品: AD9516-2BCPZ-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
AD9516-2BCPZ-REEL7-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
Data Sheet
AD9516-2
Rev. C | Page 61 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x016
[2:0]
Prescaler P
Prescaler: DM = dual modulus, and FD = fixed divide.
2
1
0
Mode
Prescaler
0
FD
Divide-by-1.
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 (2/3 mode).
0
1
DM
Divide-by-4 (4/5 mode).
1
0
DM
Divide-by-8 (8/9 mode).
1
0
1
DM
Divide-by-16 (16/17 mode).
1
0
DM
Divide-by-32 (32/33 mode) (default).
1
FD
Divide-by-3.
0x017
[7:2]
STATUS pin
Selects the signal that is connected to the STATUS pin.
control
7
6
5
4
3
2
Level or
Dynamic
Signal
Signal at STATUS Pin
0
LVL
Ground (dc) (default).
0
1
DYN
N divider output (after the delay).
0
1
0
DYN
R divider output (after the delay).
0
1
DYN
A divider output.
0
1
0
DYN
Prescaler output.
0
1
0
1
DYN
PFD up pulse.
0
1
0
DYN
PFD down pulse.
0
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active
high.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
1
0
1
LVL
Status REF1 frequency (active high).
1
0
1
0
LVL
Status REF2 frequency (active high).
1
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
LVL
Status of VCO frequency (active high).
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
0
LVL
Holdover active (active high).
1
0
1
LVL
LD pin comparator output (active high).
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency (active low).
1
0
LVL
Status of REF2 frequency (active low).
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of VCO frequency (active low).
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
Digital lock detect (DLD) (active low).
1
0
LVL
Holdover active (active low).
1
LVL
LD pin comparator output (active low).
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