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參數(shù)資料
| 型號(hào)： | AD9516-2/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9516-2 2.2GHZ |
| 產(chǎn)品培訓(xùn)模塊： | Active Filter Design Tools |
| 設(shè)計(jì)資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-2 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-2 |
| 主要屬性： | 2 輸入，14 輸出，2.2GHz VCO |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9516-2BCPZ-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP AD9516-2BCPZ-REEL7-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP |
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Data Sheet
AD9516-2
Rev. C | Page 39 of 80
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
R
E
F
E
RE
NC
E
HOLD
0
1
0
1
DIVIDE BY
2, 3, 4, 5, OR 6
06
42
1
-0
70
Figure 54. Reference and VCO Status Monitors
VCO Calibration
The AD9516 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off of a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be present.
During the first initialization after a power-up or a reset of the
AD9516, a VCO calibration sequence is initiated by setting
Register 0x018[0] = 1b. This can be done as part of the initial
setup, before executing update registers (Register 0x232[0] = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting Register 0x018[0] = 0b, executing an update
registers operation, setting Register 0x018[0] = 1b, and executing
another update registers operation. A readback bit, Bit 6 in
Register 0x01F, indicates when a VCO calibration is finished
by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is as follows:
Program the PLL registers to the proper values for the
PLL loop. Note that that automatic holdover mode
must be disabled, and the VCO divider must not be
set to “Static.”
Ensure that the input reference signal is present.
For the initial setting of the registers after a power-up or
reset, initiate VCO calibration by setting Register
0x018[0] = 1b. Subsequently, whenever a calibration is
desired, set Register 0x018[0] = 0b, update registers;
and then set Register 0x018[0] = 1b, update registers.
A SYNC operation is initiated internally, causing the
outputs to go to a static state determined by normal
SYNC function operation.
VCO calibrates to the desired setting for the requested
VCO frequency.
Internally, the SYNC signal is released, allowing
outputs to continue clocking.
PLL loop is closed.
PLL locks.
A sync is executed during the VCO calibration; therefore, the
outputs of the AD9516 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 54
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
Table 29. Example Time to Complete a VCO Calibration
with Different fREFIN Frequencies
fREFIN (MHz)
R Divider
PFD
Time to Calibrate VCO
100
1
100 MHz
88 μs
10
1 MHz
8.8 ms
10
100
100 kHz
88 ms
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參數(shù)描述 |
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| AD9516-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.0 GHz VCO |
| AD9516-3/PCBZ | 功能描述:BOARD EVAL FOR AD9516-3 2.0GHZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9516-3BCPZ | 功能描述:IC CLOCK PLL/VCO 2GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9516-3BCPZ-REEL7 | 功能描述:IC CLOCK PLL/VCO 2GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9516-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 1.6 GHz VCO |
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