參數(shù)資料
型號(hào)： AD9516-2/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 77/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9516-2 2.2GHZ
產(chǎn)品培訓(xùn)模塊： Active Filter Design Tools
設(shè)計(jì)資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-2 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9516-2
主要屬性： 2 輸入，14 輸出，2.2GHz VCO
次要屬性： CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面
已供物品： 板，線纜，CD，電源
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9516-2BCPZ-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
AD9516-2BCPZ-REEL7-ND - IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
Data Sheet
AD9516-2
Rev. C | Page 79 of 80
CMOS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9)
that are selectable as either CMOS or LVDS level outputs.
When selected as CMOS, each output becomes a pair of CMOS
outputs, each of which can be individually turned on or off and
set as noninverting or inverting. These outputs are 3.3 V CMOS
compatible.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver.
The value of the resistor is dependent on the board design and
timing requirements (typically 10 to 100 is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
CMOS
10
60.4
(1.0 INCH)
MICROSTRIP
06421-
076
Figure 75. Series Termination of CMOS Output
Termination at the far-end of the PCB trace is a second option.
The CMOS outputs of the AD9516 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 76. The far-
end termination network should match the PCB trace impedance
and provide the desired switching point. The reduced signal
swing may still meet receiver input requirements in some
applications. This can be useful when driving long trace
lengths on less critical nets.
CMOS
10
50
100
VS
06421-
077
Figure 76. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9516 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
相關(guān)PDF資料
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GCM18DRMT CONN EDGECARD 36POS .156 WW
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HK160856NK-T INDUCTOR HI FREQ 56NH 10% 0603
ECE-P2GA821HA CAP ALUM 820UF 400V 20% SNAP
GSM10DRAN CONN EDGECARD 20POS R/A .156 SLD
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