參數(shù)資料
型號(hào)： AD9516-0/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/80頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
設(shè)計(jì)資源： AD9516-0 BOM
AD9516 Eval Brd Schematic
AD9516 Gerber Files
標(biāo)準(zhǔn)包裝： 1
Data Sheet
AD9516-0
Rev. C | Page 41 of 80
To connect the LVPECL outputs directly to the internal VCO or
CLK, the VCO divider must be selected as the source to the
distribution section, even if no channel uses it.
Either the internal VCO or the CLK can be selected as the
source for the direct to output routing.
Table 31. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
Selection
0x1E1[1:0] = 00b
CLK is the source; VCO divider selected
0x1E1[1:0] = 10b
VCO is the source; VCO divider selected
0x192[1] = 1b
Direct to output OUT0, OUT1
0x195[1] = 1b
Direct to output OUT2, OUT3
0x198[1] = 1b
Direct to output OUT4, OUT5
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, 6) and the
division of the channel divider. Table 32 and Table 33 indicate
how the frequency division for a channel is set. For the LVPECL
outputs, there is only one divider per channel. For the LVDS/
CMOS outputs, there are two dividers (X.1, X.2) cascaded
per channel.
Table 32. Frequency Division for Divider 0 to Divider 2
CLK
or VCO
Selected
VCO
Divider
Channel
Divider
Direct to
Output
Frequency
Division
CLK/VCO
2 to 6
1 (bypassed)
Yes
1
CLK/VCO
2 to 6
1 (bypassed)
No
(2 to 6) × (1)
CLK/VCO
2 to 6
2 to 32
No
(2 to 6) ×
(2 to 32)
CLK
Not used
1 (bypassed)
No
1
CLK
Not used
2 to 32
No
2 to 32
Table 33. Frequency Division for Divider 3 and Divider 4
CLK
or VCO
Selected
VCO
Divider
Channel Divider
Frequency
Division
X.1
X.2
CLK/VCO
2 to 6
1
(bypassed)
1
(bypassed)
(2 to 6) ×
(1) × (1)
CLK/VCO
2 to 6
2 to 32
1
(bypassed)
(2 to 6) ×
(2 to 32) × (1)
CLK/VCO
2 to 6
2 to 32
(2 to 6) ×
(2 to 32) ×
(2 to 32)
CLK
Not used
1
CLK
Not used
2 to 32
1
(2 to 32) × (1)
CLK
Not used
2 to 32
2 to 32 ×
(2 to 32)
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 2 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 52 through Table 62).
VCO Divider
The VCO divider provides frequency division between
the internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Table 60, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving a total of
six LVPECL outputs (OUT0 to OUT5). Table 34 lists the register
locations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting
of the DCCOFF bits.
Table 34. Setting DX for Divider 0, Divider 1, and Divider 21
Divider
Low Cycles
M
High Cycles
N
Bypass
DCCOFF
0
0x190[7:4]
0x190[3:0]
0x191[7]
0x192[0]
1
0x193[7:4]
0x193[3:0]
0x194[7]
0x195[0]
2
0x196[7:4]
0x196[3:0]
0x197[7]
0x198[0]
1
Note that the value stored in the register = # of cycles minus 1.
Channel Frequency Division (0, 1, and 2)
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, DX = 1.
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 2 to 32.
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