參數(shù)資料
型號： AD9516-0/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 25/80頁
文件大小： 0K
描述： IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
設(shè)計(jì)資源： AD9516-0 BOM
AD9516 Eval Brd Schematic
AD9516 Gerber Files
標(biāo)準(zhǔn)包裝： 1
Data Sheet
AD9516-0
Rev. C | Page 31 of 80
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
1600 MHz section only in that the VCO divider (divide-by-2,
divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is
bypassed. This limits the frequency of the clock source to
<1600 MHz (due to the maximum input frequency allowed at
the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, use the register settings that are shown in Table 25.
Table 25. Settings for Clock Distribution < 1600 MHz
Register
Function
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off)
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x1E1[1] = 0b
CLK selected as the source
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
Table 26. Settings for Using Internal PLL with External VCO <
1600 MHz
Register
Function
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x010[1:0] = 00b
PLL normal operation (PLL on), along with
other appropriate PLL settings in Register 0x010
to Register 0x01E
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 27. Setting the PFD Polarity
Register
Function
0x010[7] = 0b
PFD polarity positive (higher control voltage
produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control voltage
produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
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AD9516-1BCPZ 功能描述:IC CLOCK GEN 2.5GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
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