- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16537 > AD9516-0/PCBZ (Analog Devices Inc)IC CLOCK GEN 2.8GHZ VCO 64-LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9516-0/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.8GHZ VCO 64-LFCSP |
| 設計資源： | AD9516-0 BOM AD9516 Eval Brd Schematic AD9516 Gerber Files |
| 標準包裝： | 1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
AD9516-0
Data Sheet
Rev. C | Page 40 of 80
VCO calibration must be manually initiated. This allows for
flexibility in deciding what order to program registers and when
to initiate a calibration, instead of having it happen every time
certain PLL registers have their values change. For example, this
allows for the VCO frequency to be changed by small amounts
without having an automatic calibration occur each time; this
should be done with caution and only when the user knows that
the VCO control voltage is not going to exceed the nominal best
performance limits. For example, a few 100 kHz steps are fine,
but a few MHz might not be). In addition, because the calibration
procedure results in rapid changes in the VCO frequency, the
distribution section is automatically placed in SYNC until the
calibration is finished. Therefore, this temporary loss of outputs
must be expected.
A VCO calibration should be initiated under the following
conditions:
After changing any of the PLL R, P, B, and A divider
settings, or after a change in the PLL reference clock
frequency. This, in effect, means any time a PLL register
or reference clock is changed such that a different VCO
frequency results.
Whenever system calibration is desired. The VCO is designed
to operate properly over extremes of temperatures even when
first calibrated at the opposite extreme. However, a VCO
calibration can be initiated at any time, if desired.
CLOCK DISTRIBUTION
A clock channel consists of a pair (or double pair, in the case of
CMOS) of outputs that share a common divider. A clock output
consists of the drivers that connect to the output pins. The clock
outputs have either LVPECL or LVDS/CMOS signal levels at
the pins.
The AD9516 has five clock channels: three channels are LVPECL
(six outputs); two channels are LVDS/CMOS (up to four LVDS
outputs, or up to eight CMOS outputs).
Each channel has its own programmable divider that divides
the clock frequency that is applied to its input. The LVPECL
channel dividers can divide by any integer from 2 to 32, or
the divider can be bypassed to achieve a divide by one. Each
LVDS/CMOS channel divider contains two of these divider
blocks in a cascaded configuration. The total division of the
channel is the product of the divide value of the cascaded dividers.
This allows divide values of (1 to 32) × (1 to 32), or up to 1024
(note that this is not all values from 1 to 1024 but only the set
of numbers that are the product of the two dividers).
Because the internal VCO frequency is above the maximum
channel divider input frequency (1600 MHz), the VCO divider
must be used after the on-chip VCO. The VCO divider can be
set to divide by 2, 3, 4, 5, or 6. External clock signals connected
to the CLK input also require the VCO divider if the frequency
of the signal is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function,
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or start low.
Internal VCO or External CLK as Clock Source
The clock distribution of the AD9516 has two clock input sources:
an internal VCO or an external clock connected to the CLK/
CLK pins. Either the internal VCO or CLK must be chosen as
the source of the clock signal to distribute. When the internal
VCO is selected as the source, the VCO divider must be used.
When CLK is selected as the source, it is not necessary to use
the VCO divider if the CLK frequency is less than the
maximum channel divider input frequency (1600 MHz);
otherwise, the VCO divider must be used to reduce the
frequency to one acceptable by the channel dividers. Table 30
shows how the VCO, CLK, and VCO divider are selected.
Register 0x1E1[1:0] selects the channel divider source and
determines whether the VCO divider is used. It is not possible
to select the VCO without using the VCO divider.
Table 30. Selecting VCO or CLK as Source for Channel
Divider, and Whether VCO Divider Is Used
Register 0x1E1
Channel Divider Source
VCO Divider
Bit 1
Bit 0
0
CLK
Used
0
1
CLK
Not used
1
0
VCO
Used
1
Not allowed
CLK or VCO Direct to LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs, OUT0 to OUT5. This configuration
can pass frequencies up to the maximum frequency of the VCO
directly to the LVPECL outputs. The LVPECL outputs may not
be able to provide full voltage swing at the highest frequencies.
相關PDF資料 |
PDF描述 |
|---|---|
| ESM15DSUS | CONN EDGECARD 30POS DIP .156 SLD |
| MCP112T-240E/TT | IC VOLT DET 2.32V LOW SOT-23B |
| HK1608R10K-T | INDUCTOR HI FREQ 100NH 10% 0603 |
| ECE-P2WA821HX | CAP ALUM 820UF 450V 20% SNAP |
| EGM12DTMS | CONN EDGECARD 24POS R/A .156 SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9516-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.5 GHz VCO |
| AD9516-1/PCBZ | 功能描述:BOARD EVALUATION FOR AD9516-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9516-1BCPZ | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9516-1BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9516-1XCPZ | 制造商:Analog Devices 功能描述:14-CHANNEL CLOCK GENERATOR WITH INTEGRATED 2.8 GHZ VCO - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。