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參數(shù)資料
| 型號： | AD9514/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL CLOCK 3CH AD9514 |
| 設(shè)計資源： | AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9514 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘分配 |
| 已用 IC / 零件： | AD9514 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9514BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP AD9514BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP |
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AD9514
Rev. 0 | Page 25 of 28
APPLICATIONS
USING THE AD9514 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer, and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the A/D output. Clock integrity require-
ments scale with the analog input frequency and resolution,
with higher analog input frequency applications at ≥14-bit
resolution being the most stringent. The theoretical SNR of an
ADC is limited by the ADC resolution and the jitter on the
sampling clock. Considering an ideal ADC of infinite resolution
where the step size and quantization error can be ignored, the
available SNR can be expressed approximately by
×
=
J
AT
f
SNR
2π
1
log
20
where fA is the highest analog frequency being digitized.
Tj
is the rms jitter on the sampling clock.
Figure 35 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
S
NR
(dB)
EN
OB
10
1k
100
30
40
50
60
70
80
90
100
110
05596-091
6
8
10
12
14
16
18
T
J
= 100f
S
200f
S
400f
S
1ps
2ps
10ps
SNR = 20log
1
2
πf
ATJ
Figure 35. ENOB and SNR vs. Analog Input Frequency
See Application Notes AN-756 and AN-501 at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9514 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9514 provide the lowest jitter clock signals
available from the AD9514. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. The simplified equivalent circuit in Figure 31 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 36. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the switching threshold (VS 1.3 V).
VS
LVPECL
50
Ω
50
Ω
SINGLE-ENDED
(NOT COUPLED)
VS
LVPECL
127
Ω
127
Ω
83
Ω
83
Ω
VT = VS – 1.3V
05596-
030
Figure 36. LVPECL Far-End Termination
VS
LVPECL
100
Ω DIFFERENTIAL
(COUPLED)
VS
LVPECL
100
Ω
0.1nF
200
Ω
200
Ω
05596-
031
Figure 37. LVPECL with Parallel Transmission Line
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