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參數(shù)資料
型號(hào): AD9511BCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 58/60頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時(shí)鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.2GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
AD9511
Rev. A | Page 7 of 60
TIMING CHARACTERISTICS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL
Termination = 50 Ω to VS 2 V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
Output Rise Time, tRP
130
180
ps
20% to 80%, measured differentially
Output Fall Time, tFP
130
180
ps
80% to 20%, measured differentially
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT1
Divide = Bypass
335
490
635
ps
Divide = 2 32
375
545
695
ps
Variation with Temperature
0.5
ps/°C
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part, tSKP2
70
100
140
ps
OUT1 to OUT2 on Same Part, tSKP2
15
45
80
ps
OUT0 to OUT2 on Same Part, tSKP2
45
65
90
Ps
All LVPECL OUT Across Multiple Parts, tSKP_AB3
275
ps
Same LVPECL OUT Across Multiple Parts, tSKP_AB3
130
ps
LVDS
Termination = 100 Ω differential
Output level 40h (41h) <2:1> = 01b
3.5 mA termination current
Output Rise Time, tRL
200
350
ps
20% to 80%, measured differentially
Output Fall Time, tFL
210
350
ps
80% to 20%, measured differentially
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1
Delay off on OUT4
OUT3 to OUT4
Divide = Bypass
0.99
1.33
1.59
ns
Divide = 2 32
1.04
1.38
1.64
ns
Variation with Temperature
0.9
ps/°C
OUTPUT SKEW, LVDS OUTPUTS
Delay off on OUT4
OUT3 to OUT4 on Same Part, tSKV2
85
+270
ps
All LVDS OUTs Across Multiple Parts, tSKV_AB3
450
ps
Same LVDS OUT Across Multiple Parts, tSKV_AB3
325
ps
CMOS
B outputs are inverted; termination = open
Output Rise Time, tRC
681
865
ps
20% to 80%; CLOAD = 3 pF
Output Fall Time, tFC
646
992
ps
80% to 20%; CLOAD = 3 pF
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1
Delay off on OUT4
Divide = Bypass
1.02
1.39
1.71
ns
Divide = 2 32
1.07
1.44
1.76
ns
Variation with Temperature
1
ps/°C
OUTPUT SKEW, CMOS OUTPUTS
Delay off on OUT4
OUT3 to OUT4 on Same Part, tSKC2
140
+145
+300
All CMOS OUT Across Multiple Parts, tSKC_AB3
650
ps
Same CMOS OUT Across Multiple Parts, tSKC_AB3
500
ps
LVPECL-TO-LVDS OUT
Everything the same; different logic type
Output Skew, tSKP_V
0.74
0.92
1.14
ns
LVPECL to LVDS on same part
LVPECL-TO-CMOS OUT
Everything the same; different logic type
Output Skew, tSKP_C
0.88
1.14
1.43
ns
LVPECL to CMOS on same part
LVDS-TO-CMOS OUT
Everything the same; different logic type
Output Skew, tSKV_C
158
353
506
ps
LVDS to CMOS on same part
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