參數(shù)資料
型號(hào)： AD9511BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/60頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 扇出緩沖器（分配），除法器
PLL： 是
輸入： 時(shí)鐘
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.2GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
AD9511
Rev. A | Page 33 of 60
or power-down. When the SYNCB function is selected, the
FUNCTION pin does not act as either RESETB or PDB.
PDB: 58h<6:5> = 11b
The FUNCTION pin may also be programmed to work as an
asynchronous full power-down, PDB. Even in this full power-
down mode, there is still some residual VS current because
some on-chip references continue to operate. In PDB mode, the
FUNCTION pin is active low. The chip remains in a power-
down state until PDB is returned to logic high. The chip returns
to the settings programmed prior to the power-down.
more details on what occurs during a PDB initiated power-
down.
DISTRIBUTION SECTION
As previously mentioned, the AD9511 is partitioned into two
operational sections: PLL and distribution. The PLL Section
was discussed previously. If desired, the distribution section can
be used separately from the PLL section.
CLK1 AND CLK2 CLOCK INPUTS
Either CLK1 or CLK2 may be selected as the input to the
distribution section. The CLK1 input can be connected to drive
the distribution section only. CLK1 is selected as the source for
the distribution section by setting Register 45h<0> = 1. This is
the power-up default state.
CLK1 and CLK2 work for inputs up to 1600 MHz. The jitter
performance is improved by a higher input slew rate. The input
level should be between approximately 150 mV p-p to no more
than 2 V p-p. Anything greater may result in turning on the
protection diodes on the input pins, which could degrade the
jitter performance.
See Figure 35 for the CLK1 and CLK2 equivalent input circuit.
These inputs are fully differential and self-biased. The signal
should be ac-coupled using capacitors. If a single-ended input
must be used, this can be accommodated by ac coupling to one
side of the differential input only. The other side of the input
should be bypassed to a quiet ac ground by a capacitor.
The unselected clock input (CLK1 or CLK2) should be powered
down to eliminate any possibility of unwanted crosstalk
between the selected clock input and the unselected clock input.
DIVIDERS
Each of the five clock outputs of the AD9511 has its own
divider. The divider can be bypassed to get an output at the
same frequency as the input (1×). When a divider is bypassed, it
is powered down to save power.
All integer divide ratios from 1 to 32 may be selected. A divide
ratio of 1 is selected by bypassing the divider.
Each divider can be configured for divide ratio, phase, and duty
cycle. The phase and duty cycle values that can be selected
depend on the divide ratio that is chosen.
Setting the Divide Ratio
The divide ratio is determined by the values written via the SCP
to the registers that control each individual output, OUT0 to
OUT4. These are the even numbered registers beginning at 4Ah
and going through 52h. Each of these registers is divided into
bits that control the number of clock cycles the divider output
stays high (high_cycles <3:0>) and the number of clock cycles
the divider output stays low (low_cycles <7:4>). Each value is 4
bits and has the range of 0 to 15.
The divide ratio is set by
Divide Ratio = (high_cycles + 1) + (low_cycles + 1)
Example 1:
Set the Divide Ratio = 2
high_cycles = 0
low_cycles = 0
Divide Ratio = (0 + 1) + (0 + 1) = 2
Example 2:
Set Divide Ratio = 8
high_cycles = 3
low_cycles = 3
Divide Ratio = (3 + 1) + (3 + 1) = 8
Note that a Divide Ratio of 8 may also be obtained by setting:
high_cycles = 2
low_cycles = 4
Divide Ratio = (2 + 1) + (4 + 1) = 8
Although the second set of settings produce the same divide
ratio, the resulting duty cycle is not the same.
Setting the Duty Cycle
The duty cycle and the divide ratio are related. Different divide
ratios have different duty cycle options. For example, if Divide
Ratio = 2, the only duty cycle possible is 50%. If the Divide
Ratio = 4, the duty cycle may be 25%, 50%, or 75%.
The duty cycle is set by
Duty Cycle = (high_cycles + 1)/[(high_cycles + 1) + (low_cycles + 1)]
See Table 17 for the values of the available duty cycles for each
divide ratio.
相關(guān)PDF資料
PDF描述
AD9512UCPZ-EP-R7 IC CLOCK DIST 5OUT PLL 48LFCSP
AD9512UCPZ-EP IC CLOCK DIST 5OUT PLL 48LFCSP
AD9513BCPZ-REEL7 IC CLOCK DIST 3OUT PLL 32LFCSP
AD9514BCPZ-REEL7 IC CLOCK DIST 3OUT PLL 32LFCSP
AD9515BCPZ-REEL7 IC CLOCK DIST 2OUT PLL 32LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9511-VCO/PCB 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk
AD9512 制造商:AD 制造商全稱:Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9512/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk
AD9512/PCBZ 功能描述:BOARD EVAL FOR AD9512 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9512BCPZ 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*