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參數(shù)資料
| 型號(hào)： | AD9510BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
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AD9510
Data Sheet
Rev. B | Page 40 of 56
SERIAL CONTROL PORT
The AD9510 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9510 serial control port is compatible with most synchronous
transfer formats, including both the Motorola SPI and Intel
SSR protocols. The serial control port allows read/write access
to all registers that configure the AD9510. Single or multiple
byte transfers are supported, as well as MSB first or LSB first
transfer formats. The AD9510 serial control port can be
configured for a single bidirectional input/output pin (SDIO
only) or for two unidirectional input/output pins (SDIO/SDO).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 k resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
as either an input only or as both an input/output. The AD9510
defaults to two unidirectional pins for input/output, with SDIO
used as an input, and SDO as an output. Alternatively, SDIO
can be used as a bidirectional input/output pin by writing to the
SDO enable register at Register 0x00[7] = 1b.
SDO (serial data out) is used only in the unidirectional input/
output mode (Register 0x00[7] = 0, default) as a separate output
pin for reading back data. The AD9510 defaults to this input/
output mode. Bidirectional input/output mode (using SDIO as
both input and output) can be enabled by writing to the SDO
enable register at Register 0x00[7] = 1.
CSB (chip select bar) is an active low control that gates the read
and write cycles. When CSB is high, SDO and SDIO are in a
high impedance state. This pin is internally pulled down by a
30 k resistor to ground. Do not leave it unconnected or tied
low. See the General Operation of Serial Control Port section
on the use of the CSB in a communication cycle.
Figure 44. Serial Control Port
GENERAL OPERATION OF SERIAL CONTROL PORT
Framing a Communication Cycle with CSB
Each communications cycle (a write or a read operation) is
gated by the CSB line. CSB must be brought low to initiate a
communication cycle. CSB must be brought high at the comple-
tion of a communication cycle (see Figure 52). If CSB is not
brought high at the end of each write or read cycle (on a byte
boundary), the last byte is not loaded into the register buffer.
CSB stall high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (W1:W0 must be
set to 00, 01, or 10, see Table 21). In these modes, CSB can
temporarily return high on any byte boundary, allowing time
for the system controller to process the next byte. CSB can go
high on byte boundaries only and can go high during either
part (instruction or data) of the transfer. During this period, the
serial control port state machine enters a wait state until all data
is sent. If the system controller decides to abort the transfer
before all of the data is sent, the state machine must be reset by
either completing the remaining transfer or by returning the
CSB low for at least one complete SCLK cycle (but less than
eight SCLK cycles). Raising the CSB on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In the streaming mode (W1:W0 = 11b), any number of data bytes
can be transferred in a continuous stream. The register address
is automatically incremented or decremented (see the MSB/LSB
First Transfers section). CSB must be raised at the end of the
last byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9510.
The first writes a 16-bit instruction word into the AD9510,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9510 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation (I15 = 0b), the
second part is the transfer of data into the serial control port
buffer of the AD9510. The length of the transfer (1, 2, 3 bytes, or
streaming mode) is indicated by 2 bits (W1:W0) in the instruction
byte. CSB can be raised after each sequence of 8 bits to stall the
bus (except after the last byte, where it ends the cycle). When
the bus is stalled, the serial transfer resumes when CSB is lowered.
Stalling on nonbyte boundaries resets the serial control port.
Since data is written into a serial control port buffer area, not
directly into the actual control registers of the AD9510, an addi-
tional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9510,
thereby causing them to take effect. This update command
consists of writing to Register 0x5A[0] = 1b. This update bit is
self-clearing (it is not required to write 0 to it to clear it). Since
any number of bytes of data can be changed before issuing an
update command, the update simultaneously enables all register
changes since any previous update.
Phase offsets or divider synchronization do not become
effective until a SYNC is issued (see the Single-Chip
Synchronization section).
05046-017
SCLK (PIN 18)
SDIO (PIN 19)
SDO (PIN 20)
CSB (PIN 21)
AD9510
SERIAL
CONTROL
PORT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9511 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9511BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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