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參數(shù)資料
| 型號(hào)： | AD9510BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
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Data Sheet
AD9510
Rev. B | Page 37 of 56
Phase offsets can be related to degrees by calculating the phase
step for a particular divide ratio:
Phase Step = 360°/(Divide Ratio) = 360°/DIV
Using some of the same examples,
DIV = 4
Phase Step = 360°/4 = 90°
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
180°, 270°
DIV = 7
Phase Step = 360°/7 = 51.43°
Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°,
102.86°, 154.29°, 205.71°, 257.15°, 308.57°
DELAY BLOCK
OUT5 and OUT6 (LVDS/CMOS) include an analog delay element
that can be programmed (from Register 0x34 to Register 0x3A)
to give variable time delays (Δt) in the clock signal passing
through that output.
Figure 40. Analog Delay (OUT5 and OUT6)
The amount of delay that can be used is determined by the
frequency of the clock being delayed. The amount of delay can
approach one-half cycle of the clock period. For example, for a
10 MHz clock, the delay can extend to the full 8 ns maximum of
which the delay element is capable. However, for a 100 MHz
clock (with 50% duty cycle), the maximum delay is less than
5 ns (or half of the period).
OUT5 and OUT6 allow a full-scale delay in the range 1 ns to
8 ns. The full-scale delay is selected by choosing a combination
of ramp current and the number of capacitors by writing the
appropriate values into Register 0x35 and Register 0x39. There
are 25 fine delay settings (Register 0x36 and Register 0x3A =
00000b to 11000b) for each full scale, set by Register 0x36 and
Register 0x3A.
This path adds some jitter greater than that specified for the
nondelay outputs. Therefore, use the delay function primarily
for clocking digital chips, such as FPGA, ASIC, DUC, and
DDC, rather than for data converters. The jitter is higher for
long full scales (~8 ns). This is because the delay block uses a
ramp and trip points to create the variable delay. A longer ramp
means more noise can be introduced.
Calculating the Delay
The following values and equations are used to calculate the
delay of the delay block.
Value of Ramp Current Control Bits (Register 0x35 or
Register 0x39 [2:0]) = IRAMP_BITS
IRAMP (A) = 200 × (IRAMP_BITS + 1)
No. of Caps = No. of 0s + 1 in Ramp Control Capacitor
(Register 0x35 or Register 0x39 [5:3]), that is, 101 = 1 + 1 =
2; 110 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1)
DELAY_RANGE (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) ×
1.3286
( )
(
)
6
1
10
1600
0.34
ns
4
×
+
×
+
=
RAMP
I
Caps
of
No.
I
Offset
DELAY_FULL_SCALE (ns) = DELAY_RANGE × (24/31) +
Offset
FINE_ADJ = Value of Delay Fine Adjust (Register 0x36 or
Register 0x3A[5:1]), that is, 11000 = 24
Delay (ns) = Offset + DELAY_RANGE × FINE_ADJ × (1/31)
OUTPUTS
The AD9510 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL only.
OUT4 to OUT7 can be selected as either LVDS or CMOS. Each
output can be enabled or turned off as needed to save power.
The simplified equivalent circuit of the LVPECL outputs is
shown in Figure 41.
Figure 41. LVPECL Output Simplified Equivalent Circuit
Figure 42. LVDS Output Simplified Equivalent Circuit
05046-
036
ΔT
FINE DELAY ADJUST
(25 STEPS)
FULL-SCALE: 1ns TO 8ns
OUT5
OUT6 ONLY
CLOCK INPUT
÷N
SELECT
M
UX
LVDS
CMOS
OUTPUT
DRIVER
05046-037
3.3V
OUT
OUTB
GND
05046-038
3.5mA
OUT
OUTB
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| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
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