參數資料
| 型號： | AD9432BSVZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 80MSPS 52TQFP |
| 標準包裝： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 80M |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 1W |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-TQFP 裸露焊盤 |
| 供應商設備封裝： | 52-TQFP-EP（10x10） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 2 個單端，單極；2 個差分，單極 |
AD9432
Rev. F | Page 14 of 16
DIGITAL OUTPUTS
The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL-/CMOS-
compatible for lower power consumption. The output data
format is twos complement (see Table 6).
Table 6. Twos Complement Output Coding (VREF = 2.5 V)
Code
AIN AIN (V)
Digital Output
+2047
1.000
0111 1111 1111
…
0
0000 0000 0000
1
0.00049
1111 1111 1111
…
2048
1.000
1000 0000 0000
The out-of-range (OR) output is logic low for normal operation.
During any clock cycle when the ADC output data (Dx) reaches
positive or negative full scale (+2047 or 2048), the OR output
goes high. The OR output is internally generated each clock cycle.
It has the same pipeline latency and propagation delay as the ADC
output data and remains high until the output data reflects an
in-range condition. The ADC output bits (Dx) do not roll over
and, therefore, remain at positive or negative full scale (+2047
or 2048) while the OR output is high.
VOLTAGE REFERENCE
A stable and accurate 2.5 V voltage reference is built into the
AD9432 (VREFOUT). In normal operation, the internal refer-
ence is used by strapping Pin 45 to Pin 46 and placing a 0.1 μF
decoupling capacitor at VREFIN.
The input range can be adjusted by varying the reference voltage
applied to the AD9432. No appreciable degradation in performance
occurs when the reference is adjusted ±5%. The full-scale range
of the ADC tracks reference voltage changes linearly.
TIMING
The AD9432 provides latched data outputs, with 10 pipeline
delays. Data outputs are included or available one propagation
delay (tPD) after the rising edge of the encode command (see
Figure 2). The length of the output data lines and the loads
placed on them should be minimized to reduce transients
within the AD9432; these transients can detract from the
dynamic performance of the converter.
The minimum guaranteed conversion rate of the AD9432 is
1 MSPS. At internal clock rates below 1 MSPS, dynamic perfor-
mance may degrade. Therefore, input clock rates below 1 MHz
should be avoided.
During initial power-up, or whenever the clock to the AD9432
is interrupted, the output data will not be accurate for 200 ns or
10 clock cycles, whichever is longer.
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相關代理商/技術參數 |
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| AD9432BSVZ-801 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 80 MSPS/105 MSPS ADC |
| AD9432PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit |
| AD9433 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9433/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9433BSQ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 105 MSPS ADC - Bulk |
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