參數(shù)資料
型號(hào): AD9432BSVZ-80
廠商: Analog Devices Inc
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS 52TQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-TQFP-EP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)差分,單極
AD9432
Rev. F | Page 11 of 16
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity (DNL)
The deviation of any code from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
measured SNR based on the following equation:
02
.
6
log
20
dB
76
.
1
+
=
Amplitude
Input
Amplitude
Scale
Full
SNR
ENOB
MEASURED
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the encode
pulse should be left in the Logic 1 state to achieve the rated per-
formance. Pulse width low is the minimum amount of time that
the encode pulse should be left in the Logic 0 state. At a given clock
rate, these specifications define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude fundamental frequency
to the rms signal amplitude of a single harmonic component
(second, third, and so on); reported in dBc.
Integral Nonlinearity (INL)
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Maximum Conversion Rate
The maximum encode rate at which parametric testing is
performed.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD) Ratio
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral com-
ponents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(degrades as signal level is lowered) or in dBFS (always related
back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the worst third-order intermodulation product;
reported in dBc. Products are located at 2f1 f2 and 2f2 f1.
Two-Tone SFDR
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the peak spurious component. The peak spurious com-
ponent may or may not be an IMD product. May be reported in
dBc (degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second-order and
third-order harmonic); reported in dBc.
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