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參數(shù)資料
| 型號： | AD9286BCPZRL7-500 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 48LFCSP |
| 標準包裝： | 750 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，雙極 |
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Data Sheet
AD9286
Rev. B | Page 21 of 28
HARDWARE INTERFACE
The pins described in Table 10 constitute the physical interface
between the programming device of the user and the serial port
of the AD9286. The SCLK and CSB pins function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9286 to prevent these signals from transitioning at the
converter inputs during critical sampling periods.
SDIO/PWDN serves a dual function when the SPI interface is
not being used. When the pin is strapped to AVDD or ground
during device power-on, it is associated with a specific function.
The mode selection table (see Table 11) describes the strappable
functions that are supported on the AD9286.
Table 11. Mode Selection
Pin
External
Voltage
Configuration
SDIO/PWDN
AVDD (default)
Chip in full power-down
AGND
Normal operation
OE
AVDD
Outputs in high impedance
AGND (default)
Outputs enabled
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/PWDN pin serves as a standalone, CMOS-compatible
control pin. When the device is powered up, it is assumed that
the user intends to use the SDIO, SCLK, and CSB pins as static
control lines for the output enable and power-down feature control.
In this mode, connecting the CSB chip select to AVDD disables
the serial port interface.
SPI ACCESSIBLE FEATURES
Table 12 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9286 part-specific features are described in
detail in Table 13.
Table 12. Features Accessible Using the SPI
Feature
Description
Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to access the DCS via the SPI
Offset
Allows the user to digitally adjust the converter
offset
Test I/O
Allows the user to set test modes to have known
data on output bits
Output Mode
Allows the user to set up outputs
Output Phase
Allows the user to set the output clock polarity
Output Delay
Allows the user to vary the DCO delay
Voltage
Reference
Allows the user to set the voltage reference
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