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參數(shù)資料
型號: AD9286BCPZRL7-500
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大小: 0K
描述: IC ADC 8BIT SPI/SRL 500M 48LFCSP
標準包裝: 750
位數(shù): 8
采樣率(每秒): 500M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 2
功率耗散(最大): 330mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,雙極
AD9286
Data Sheet
Rev. B | Page 18 of 28
The magnitude of the offset spur (OS) is shown in Equation 6.
OSOFFSET (dBFS) = 20 × log(OFFSET × 2/2RESOLUTION)
(6)
where:
OFFSET is the channel-to-channel offset in codes.
RESOLUTION is the resolution of the converter (eight bits).
OSOFFSET, as a function of offset mismatch, is shown in Figure 32.
60
55
50
45
40
35
30
25
20
0
2.5
2.0
1.5
1.0
0.5
O
F
SET
SPU
R
(d
B
F
S)
OFFSET MISMATCH (% FS)
09338-
034
Figure 32. OSOFFSET as a Function of Offset Mismatch
Due to the orthogonal relationship between the gain and timing
errors, it is impossible to correct for one with the other. To mini-
mize channel-to-channel gain error, the AD9286 is designed
to have very close gain matching between the two channels.
Address 0x37 and Address 0x38 of the SPI provide the ability to
add delay to either clock path to realize a minimum clock skew
error. Also provided via the SPI, in Address 0x10, is the ability
to minimize the channel-to-channel offset error.
DIGITAL OUTPUTS
Digital Output Enable Function (OE)
The AD9286 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OE pin. When OE
is set to logic level high, the output drivers for both data buses
are placed into a high impedance state.
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