AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
參數(shù)資料
型號(hào): AD9272BSVZ-80
廠商: Analog Devices Inc
文件頁數(shù): 44/44頁
文件大?。?/td> 0K
描述: IC ADC OCT 12BIT 80MSPS 100-TQFP
設(shè)計(jì)資源: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
特色產(chǎn)品: AD9272: Octal LNA/VGA/AAF/ADC and Crosspoint Switch
標(biāo)準(zhǔn)包裝: 1
類型: AAF,ADC,交叉點(diǎn)開關(guān),LNA,VGA
分辨率(位): 12 b
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 1.8V,3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 780 (CN2011-ZH PDF)
配用: AD9272-65EBZ-ND - BOARD EVAL AD9272
AD9272
Rev. C | Page 9 of 44
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3.
Parameter1
Temp
Min
Typ
Max
Unit
Clock Rate
Full
10
80
MSPS
Clock Pulse Width High (tEH)
Full
6.25
ns
Clock Pulse Width Low (tEL)
Full
6.25
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO± Propagation Delay (tFCO)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
DCO± Propagation Delay (tCPD)4
Full
tFCO + (tSAMPLE/24)
ns
DCO± to Data Delay (tDATA)4
Full
(tSAMPLE/24) 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
DCO± to FCO± Delay (tFRAME)4
Full
(tSAMPLE/24) 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
Data-to-Data Skew
(tDATA-MAX tDATA-MIN)
Full
±100
±350
ps
Wake-Up Time (Standby), GAIN+ = 0.8 V
25°C
2
μs
Wake-Up Time (Power-Down)
25°C
1
ms
Pipeline Latency
Full
8
Clock cycles
APERTURE
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
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