參數(shù)資料
型號： AD9272BSVZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 25/44頁
文件大小： 0K
描述： IC ADC OCT 12BIT 80MSPS 100-TQFP
設(shè)計(jì)資源： Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
特色產(chǎn)品： AD9272: Octal LNA/VGA/AAF/ADC and Crosspoint Switch
標(biāo)準(zhǔn)包裝： 1
類型： AAF，ADC，交叉點(diǎn)開關(guān)，LNA，VGA
分辨率（位）： 12 b
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行
電壓電源： 模擬和數(shù)字
電源電壓： 1.8V，3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 780 (CN2011-ZH PDF)
配用： AD9272-65EBZ-ND - BOARD EVAL AD9272
AD9272
Rev. C | Page 31 of 44
ADC
The AD9272 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and output clocks.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9272 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 54 shows the preferred method for clocking the AD9272.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50 MHz, is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9272 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9272, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2812
3.3V
50 100
CLK–
CLK+
ADC
AD9272
MINI-CIRCUITS
ADT1-1WT, 1:1Z
XFMR
VFAC3
OUT
0
70
29
-05
0
Figure 54. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 55. The AD951x family of clock drivers offers excellent
jitter performance.
100
0.1F
240
AD951x FAMILY
50*
CLK
*50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
PECL DRIVER
3.3V
OUT
VFAC3
0
7029
-05
1
Figure 55. Differential PECL Sample Clock
100
0.1F
AD951x FAMILY
50*
CLK
*50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
LVDS DRIVER
3.3V
OUT
VFAC3
0
7029
-05
2
Figure 56. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 57). Although the
CLK+ input circuit supply is AVDDx (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1F
39k
CMOS DRIVER
50*
OPTIONAL
100
0.1F
CLK
*50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
AD951x FAMILY
3.3V
OUT
VFAC3
07
02
9-
0
53
Figure 57. Single-Ended 1.8 V CMOS Sample Clock
0.1F
CMOS DRIVER
50*
OPTIONAL
100
0.1F
CLK
*50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
AD951x FAMILY
3.3V
OUT
VFAC3
07
02
9-
0
54
0.1F
Figure 58. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9272 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9272. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See Table 17 for more details on
using this feature.
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