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參數(shù)資料
| 型號： | AD9272BSVZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC OCT 12BIT 80MSPS 100-TQFP |
| 設(shè)計(jì)資源： | Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135) |
| 特色產(chǎn)品： | AD9272: Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | AAF，ADC，交叉點(diǎn)開關(guān)，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8V，3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
| 配用： | AD9272-65EBZ-ND - BOARD EVAL AD9272 |
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AD9272
Rev. C | Page 32 of 44
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 59).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9272.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
NR
(
d
B
)
07
02
9-
03
8
0.25ps
Figure 59. Ideal SNR vs. Analog Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 61, the power dissipated by the AD9272 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
400
0
SAMPLING FREQUENCY (MSPS)
CURR
E
NT
(
m
A)
350
300
250
200
150
100
50
10
30
20
40
50
60
70
80
0
702
9-
0
32
IAVDD1, 80MSPS SPEED GRADE
IAVDD1, 65MSPS SPEED GRADE
IAVDD1, 40MSPS SPEED GRADE
IDRVDD
Figure 60. Supply Current vs. fSAMPLE for fIN = 5 MHz
220
170
0
SAMPLING FREQUENCY (MSPS)
P
O
W
E
R
/C
HANNE
L
(
m
W
)
10
30
20
50
40
60
80
70
215
210
205
200
195
190
185
180
175
07
02
9-
03
1
80MSPS SPEED GRADE
65MSPS SPEED GRADE
40MSPS SPEED GRADE
Figure 61. Power per Channel vs. fSAMPLE for fIN = 5 MHz
The AD9272 features scalable LNA bias currents (see Register 0x12
in Table 17). The default LNA bias current settings are high.
Figure 62 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended to adjust the LNA offset
using Register 0x10 in Table 17 when the LNA bias setting is low.
0
50
100
150
200
250
300
350
400
HIGH
L
NA
BI
AS
S
E
T
IN
G
MID-HIGH
MID-LOW
LOW
TOTAL AVDD2 CURRENT (mA)
07
029
-11
9
Figure 62. AVDD2 Current at Different LNA Bias Settings, AD9272-40
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| AD9272BSVZ-801 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9272BSVZRL-40 | 功能描述:IC ADC ASD OCTAL 40MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
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| AD9272BSVZRL-65 | 功能描述:IC ADC ASD OCTAL 65MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD9272BSVZRL-651 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
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