參數(shù)資料
型號(hào)： AD9272BSVZ-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/44頁(yè)
文件大?。?/td> 0K
描述： IC ADC OCT 12BIT 80MSPS 100-TQFP
設(shè)計(jì)資源： Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
特色產(chǎn)品： AD9272: Octal LNA/VGA/AAF/ADC and Crosspoint Switch
標(biāo)準(zhǔn)包裝： 1
類型： AAF，ADC，交叉點(diǎn)開(kāi)關(guān)，LNA，VGA
分辨率（位）： 12 b
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行
電壓電源： 模擬和數(shù)字
電源電壓： 1.8V，3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 780 (CN2011-ZH PDF)
配用： AD9272-65EBZ-ND - BOARD EVAL AD9272
AD9272
Rev. C | Page 30 of 44
GAIN–
50
GAIN+
AD9272
AVDD2
31.3k
10k
0.01F
±0.4DC AT
0.8V CM
±0.4DC AT
0.8V CM
100
499
±0.8V DC
0.01F
100
499
523
499
0.8V CM
AD8138
0702
9-
0
98
Figure 52. Differential GAIN± Pins Configuration
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. The
input-referred noise of the LNA limits the minimum resolvable
input signal, whereas the output-referred noise, which depends
primarily on the VGA, limits the maximum instantaneous
dynamic range that can be processed at any one particular gain
control voltage. This latter limit is set in accordance with the
total noise floor of the ADC.
Output-referred noise as a function of GAIN+ is shown in
Figure 14 for the short-circuit input conditions. The input
noise voltage is simply equal to the output noise divided by
the measured gain at each point in the control range.
The output-referred noise is a flat 60 nV/√Hz (postamp gain =
24 dB) over most of the gain range because it is dominated by
the fixed output-referred noise of the VGA. At the high end of
the gain control range, the noise of the LNA and of the source
prevail. The input-referred noise reaches its minimum value
near the maximum gain control voltage, where the input-
referred contribution of the VGA is miniscule.
At lower gains, the input-referred noise, and therefore, the noise
figure, increases as the gain decreases. The instantaneous
dynamic range of the system is not lost, however, because the
input capacity increases as the input-referred noise increases.
The contribution of the ADC noise floor has the same dependence.
The important relationship is the magnitude of the VGA output
noise floor relative to that of the ADC.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and is usually evident only when a large signal is
present. The gain interface includes an on-chip noise filter, which
significantly reduces this effect at frequencies above 5 MHz. Care
should be taken to minimize noise impinging at the GAIN±
inputs. An external RC filter can be used to remove VGAIN source
noise. The filter bandwidth should be sufficient to accommodate
the desired control bandwidth.
Antialiasing Filter
The filter that the signal reaches prior to the ADC is used to
reject dc signals and to band limit the signal for antialiasing.
Figure 53 shows the architecture of the filter.
The antialaising filter is a combination of a single-pole high-
pass filter and a second-order low-pass filter. The high-pass
filter can be configured at a ratio of the low-pass filter cutoff.
This is selectable through the SPI.
The filter uses on-chip tuning to trim the capacitors and in turn
set the desired cutoff frequency and reduce variations. The
default 3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC
sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1,
1.2, or 1.3 times this frequency through the SPI. The cutoff
tolerance is maintained from 8 MHz to 18 MHz.
30C
4C
30C
C
C = 0.8pF TO 5.1pF
n = 0 TO 7
10k/n
0
70
29
-11
0
4k
2k
4k
2k
C
Figure 53. Simplified Filter Schematic
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled and disabled
through the SPI. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming
the filter cutoff scaling or ADC sample rate. Occasional
retuning during an idle time is recommended to compensate
for temperature drift.
There is a total of eight SPI-programmable settings that allow the
user to vary the high-pass filter cutoff frequency as a function
of the low-pass cutoff frequency. Two examples are shown in
Table 10: one is for an 8 MHz low-pass cutoff frequency and the
other is for an 18 MHz low-pass cutoff frequency. In both cases,
as the ratio decreases, the amount of rejection on the low-end
frequencies increases. Therefore, making the entire AAF
frequency pass band narrow can reduce low frequency noise or
maximize dynamic range for harmonic processing.
Table 10. SPI-Selectable High-Pass Filter Cutoff Options
High-Pass Cutoff
SPI Setting
Ratio1
Low-Pass Cutoff
= 8 MHz
Low-Pass Cutoff
= 18 MHz
0
20.65
387 kHz
872 kHz
1
11.45
698 kHz
1.571 MHz
2
7.92
1.010 MHz
2.273 MHz
3
6.04
1.323 MHz
2.978 MHz
4
4.88
1.638 MHz
3.685 MHz
5
4.10
1.953 MHz
4.394 MHz
6
3.52
2.270 MHz
5.107 MHz
7
3.09
2.587 MHz
5.822 MHz
1 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.
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