參數(shù)資料
型號: AD9246BCPZRL7-105
廠商: Analog Devices Inc
文件頁數(shù): 18/44頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 105MSPS 48-LFCSP
設(shè)計(jì)資源: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 350mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
AD9246
Rev. A | Page 25 of 44
MEMORY MAP REGISTER TABLE
Table 15. Memory Map Register
Addr.
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default Notes/
Comments
Chip Configuration Registers
00
chip_port_config
0
LSB first
0 = Off
(Default)
1 = On
Soft reset
0 = Off
(Default)
1 = On
1
Soft reset
0 = Off
(Default)
1 = On
LSB first
0 = Off
(Default)
1 = On
0
0x18
The nibbles
should be
mirrored. See the
01
chip_id
8-bit Chip ID Bits 7:0
(AD9246 = 0x00), (default)
Read
only
Default is unique
chip ID, different
for each device.
02
chip_grade
Open
Child ID
0 = 125
MSPS,
1 = 105
MSPS
Open
Read
only
Child ID used to
differentiate
speed grades.
Device Index and Transfer Registers
FF
device_update
Open
SW transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
Global ADC Functions
08
modes
Open
PDWN
0—full
(Default)
1—standby
Open
Internal power-down mode
000—normal (power-up, Default)
001—full power-down
010—standby
011—normal (power-up)
Note: External PDWN pin overrides
this setting.
0x00
Determines
various generic
modes of chip
operation. See
the
Mode section
and the
section.
09
clock
Open
Duty cycle
stabilizer
0—disabled
1— enabled
(Default)
0x01
See the
section and the
section.
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