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參數(shù)資料
| 型號： | AD9246BCPZRL7-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 105MSPS 48-LFCSP |
| 設(shè)計(jì)資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 350mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9246
Rev. A | Page 19 of 44
0.1F
SCHOTTKY
DIODES:
HSMS2812
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9246
MIN-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
05
49
1-
0
4
8
Figure 46. Transformer Coupled Differential Clock
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 47. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers excel-
lent jitter performance.
100
0.1F
240
AD951x
PECL DRIVER
501
CLK
150 RESISTORS ARE OPTIONAL
CLK–
CLK+
ADC
AD9246
CLOCK
INPUT
CLOCK
INPUT
054
91
-0
49
Figure 47. Differential PECL Sample Clock
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 48. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offers excellent jitter performance.
100
0.1F
501
AD951x
LVDS DRIVER
501
CLK
150 RESISTORS ARE OPTIONAL
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD9246
05491
-05
0
Figure 48. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK pin to ground using a 0.1 μF capacitor in parallel with a
39 kΩ resistor (see Figure 49). CLK+ may be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK pin with a 0.1 μF capacitor in parallel
with a 39 kΩ resistor (see Figure 49) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see Figure 50).
OPTIONAL
100
0.1F
39k
AD951x
CMOS DRIVER
501
150 RESISTOR IS OPTIONAL
CLK–
CLK+
ADC
AD9246
VCC
1k
CLOCK
INPUT
054
91-
051
Figure 49. Single-Ended 1.8 V CMOS Sample Clock
150 RESISTOR IS OPTIONAL
OPTIONAL
100
0.1F
VCC
AD951x
CMOS DRIVER
501
CLK–
CLK+
ADC
AD9246
1k
CLOCK
INPUT
05
49
1-
0
52
Figure 50. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9246 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling, or falling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9246. Noise and distortion performance are nearly flat
for a wide range of duty cycles when the DCS is on, as shown in
Jitter in the rising edge of the input is still of paramount
concern and is not reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that needs to be considered in applications
where the clock rate can change dynamically. This requires a
wait time of 1.5 μs to 5 μs after a dynamic clock frequency
increase (or decrease) before the DCS loop is relocked to the
input signal. During the time period the loop is not locked, the
DCS loop is bypassed, and the internal device timing is
dependent on the duty cycle of the input clock signal. In such
an application, it may be appropriate to disable the duty cycle
stabilizer. In all other applications, enabling the DCS circuit is
recommended to maximize ac performance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9246BCPZRL7-125 | 功能描述:IC ADC 14BIT 125MSPS 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9246BCPZRL7-80 | 制造商:Analog Devices 功能描述:14-BIT, 80 MSPS/105 MSPS/125 MSPS, 1.8 V ANALOG-TO-DIGITAL C - Tape and Reel |
| AD9248 | 制造商:Analog Devices 功能描述:40 MSPS DUAL A/D CONVERTER - Bulk |
| AD9248-20PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248-40PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
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