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參數(shù)資料
| 型號： | AD8324ACP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3 V Upstream Cable Line Driver |
| 中文描述： | LINE DRIVER, QCC20 |
| 封裝： | 4 X 4 MM, MO-220VGGD-1, CSP-20 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 516K |
| 代理商： | AD8324ACP-REEL7 |
AD8324
Rev. 0 | Page 4 of 16
1
TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.
2
Guaranteed by design and characterization to ±6 sigma for T
A
= 25°C.
3
Guaranteed by design and characterization to ±3 sigma for T
A
= 25°C.
4
Measured through a 1:1 transformer.
5
Specification is worst case over all gain codes.
6
V
IN
= 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
Table 2. DATEN, CLK, SDATA, TXEN, SLEEP, V
CC
= 3.3 V, unless otherwise noted
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (V
INH
= 3.3 V), CLK, SDATA, DATEN
Logic 0 Current (V
INL
= 0 V), CLK, SDATA, DATEN
Logic 1 Current (V
INH
= 3.3 V), TXEN
Logic 0 Current (V
INL
= 0 V), TXEN
Logic 1 Current (V
INH
= 3.3 V), SLEEP
Logic 0 Current (V
INL
= 0 V), SLEEP
TIMING REQUIREMENTS
Table 3. V
CC
= 3.3 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz, unless otherwise noted
Parameter
Clock Pulse Width (t
WH
)
Clock Period (t
C
)
Setup Time SDATA vs. Clock (t
DS
)
Setup Time DATEN vs. Clock (t
ES
)
Hold Time SDATA vs. Clock (t
DH
)
Hold Time DATEN vs. Clock (t
EH
)
Input Rise and Fall Times, SDATA, DATEN, Clock (t
R
, t
F
)
Min
2.1
0
0
600
50
250
50
250
Typ
Max
3.3
0.8
20
100
190
30
190
30
Unit
V
V
nA
nA
μA
μA
μA
μA
Min
16.0
32.0
5.0
15.0
5.0
3.0
Typ
Max
10
Unit
ns
ns
ns
ns
ns
ns
ns
t
DS
CLK
VALID DATA WORD G1
MSB . . . LSB
SDATA
DATEN
TXEN
ANALOG
OUTPUT
VALID DATA WORD G2
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
SIGNAL AMPLITUDE (p-p)
t
C
t
VUH
t
ES
t
EH
t
OFF
t
GS
t
CN
0
Figure 3. Serial Interface Timing
CLK
SDATA
MSB
MSB-1
MSB-2
VALID DATA BIT
t
DS
t
DH
0
Figure 4. SDATA Timng
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