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參數(shù)資料
| 型號： | AD8324ACP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3 V Upstream Cable Line Driver |
| 中文描述： | LINE DRIVER, QCC20 |
| 封裝： | 4 X 4 MM, MO-220VGGD-1, CSP-20 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 516K |
| 代理商： | AD8324ACP-REEL7 |
AD8324
APPLICATIONS
GENERAL APPLICATIONS
The AD8324 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (data over cable service
interface specification) certified cable modems and CATV set-
top boxes. The upstream signal is either a QPSK or QAM signal
generated by a DSP, a dedicated QPSK/QAM modulator, or a
DAC. In all cases, the signal must be low-pass filtered before
being applied to the PA in order to filter out-of-band noise and
higher order harmonics from the amplified signal.
Rev. 0 | Page 10 of 16
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the
output power by applying gain or attenuation. The ability to
vary the output power of the AD8324 ensures that the signal
from the cable modem will have the proper level once it arrives
at the head-end. The upstream signal path commonly includes a
diplexer and cable splitters. The AD8324 has been designed to
overcome losses associated with these passive components in
the upstream cable path.
CIRCUIT DESCRIPTION
The AD8324 is composed of three analog functions in the
transmit-enable mode. The input amplifier (preamp) can be
used in a single-ended or differential configuration. If the input
is used in the differential configuration, the input signals should
be 180 degrees out of phase and of equal amplitude. A vernier is
used in the input stage for controlling the fine 1 dB gain steps.
This stage then drives a DAC, which provides the bulk of the
AD8324’s attenuation. The signals in the preamp and DAC
blocks are differential to improve the PSRR and linearity. A
differential current is fed from the DAC into the output stage.
The output stage maintains 75 differential output impedance
in all power modes.
GAIN PROGRAMMING FOR THE AD8324
The AD8324 features a serial peripheral interface (SPI) for
programming the gain code settings. The SPI interface consists
of three digital data lines: CLK, DATEN, and SDATA. The
DATEN pin should be held low while the AD8324 is being
programmed. The SDATA pin accepts the serial data stream for
programming the AD8324 gain code. The CLK pin accepts the
clock signal to latch in the data from the SDATA line.
The AD8324 utilizes a 6-bit shift register for clocking in the
data. The shift register is designed to be programmed MSB first.
The timing interface for programming the AD8324 can be seen
in Table 2, Table 3, Figure 3, and Figure 4. While the DATEN pin
is held low, the serial bits on the SDATA line are shifted into the
register on the rising edge of the CLK pin. For existing software
that uses 8-bits to program the cable driver, the 2 MSBs will be
ignored. This allows the AD8324 to be compatible with some
existing system designs.
The AD8324 recognizes gain codes 1 through 60 (all gain codes
are in decimal, unless otherwise noted). When the AD8324 is
programmed with 61 to 63, it will internally default to max gain
(gain code 60). If the programmed gain code is above 63, the
AD8324 will recognize only the 6 LSBs. For example, gain code
75 (01001011 binary) will be interpreted as gain code 11
(001011 binary) since the 2 MSBs are ignored.
The programming range of the AD8324 is from –25.5 dB (gain
code 1) to +33.5 dB (gain code 60). The 60 dB gain range is
linear with a 1 dB change in a 1 LSB change in gain code.
Figure 15 illustrates the gain step size of the AD8324 versus gain
code. The AD8324 was characterized with a differential input
signal and a TOKO 458PT-1457 1:1 transformer at the output.
INPUT BIAS, IMPEDANCE, AND TERMINATION
The V
IN+
and V
IN–
inputs have a dc bias level of V
CC
/2; therefore
the input signal should be ac-coupled as seen in the typical
application circuit (Figure 23). The differential input impedance
of the AD8324 is approximately 1.1 k, while the single-ended
input is 550 . The high input impedance of the AD8324 allows
flexibility in termination and properly matching filter networks.
The AD8324 will exhibit optimum performance when driven
with a pure differential signal.
OUTPUT BIAS, IMPEDANCE, AND TERMINATION
.
The output stage of the AD8324 requires a bias of 3.3 V. The
3.3 V power supply should be connected to the center tap of the
output transformer. Also, the V
CC
that is being applied to the
center tap of the transformer should be decoupled as seen in the
typical application circuit (Figure 23).
The output impedance of the AD8324 is 75 , regardless of
whether the amplifier is in transmit enable, transmit disable, or
sleep mode. This, when combined with a 1:1 voltage ratio trans-
former, eliminates the need for external back termination resis-
tors. If the output signal is being evaluated using standard 50
test equipment, a minimum loss 75 to 50 pad must be used
to provide the test circuit with the proper impedance match.
The AD8324 evaluation board provides a convenient means to
implement a matching attenuator. Soldering a 43.3 resistor in
the R15 placeholder and an 86.6 resistor in the R16 place-
holder will allow testing on a 50 system. When using a
matching attenuator, it should be noted that there will be 5.7 dB
of power loss (7.5 dB voltage) through the network.
相關PDF資料 |
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| AD8324JRQ | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ-EVAL | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ-REEL | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ-REEL7 | 3.3 V Upstream Cable Line Driver |
| AD8328 | 5 V Upstream Cable Line Driver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD8324ACPZ | 功能描述:IC LINE DRIVER CATV 3.3V 20LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標準包裝:250 系列:- 類型:電平移位器 應用:LCD 電視機/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應商設備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| AD8324ACPZ-REEL7 | 功能描述:IC LINE DRIVER CATV 3.3V 20LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8324JRQ | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin QSOP Tube 制造商:Rochester Electronics LLC 功能描述:LOW COST 3.3V CABLE LINE DRIVER - Bulk 制造商:Analog Devices 功能描述:CABLE LINE DRIVER 3.3V SMD 8324 |
| AD8324JRQ-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.3 V Upstream Cable Line Driver |
| AD8324JRQ-REEL | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin QSOP T/R 制造商:Analog Devices 功能描述:SP AMP LINE DRVR AMP SGL 3.47V 20QSOP - Tape and Reel |
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