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參數(shù)資料
| 型號： | AD8324ACP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3 V Upstream Cable Line Driver |
| 中文描述： | LINE DRIVER, QCC20 |
| 封裝： | 4 X 4 MM, MO-220VGGD-1, CSP-20 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 516K |
| 代理商： | AD8324ACP-REEL7 |
AD8324
The BYP pin is used to decouple the output stage to ground.
Typically, for normal DOCSIS operation, the BYP pin should be
decoupled to ground with a 0.1 μF capacitor. However, in
applications that may require transient on/off times faster than
2 μs, smaller capacitors may be used, but it should be noted that
the BYP pin should always be decoupled to ground.
Rev. 0 | Page 12 of 16
POWER SAVING FEATURES
The AD8324 incorporates three distinct methods of reducing
power consumption: transmit disable and sleep modes for
between-burst and shutdown modes, as well as gain dependent
quiescent current for transmit enable mode.
The asynchronous TXEN pin is used to place the AD8324 into
between-burst mode. In this reduced current state, the 75
output impedance is maintained. Applying Logic 0 to the TXEN
pin deactivates the on-chip amplifier, providing a 98.8% reduc-
tion in consumed power. For 3.3 V operation, the supply current
is typically reduced from 207 mA to 2.5 mA. In this mode of
operation, between-burst noise is minimized and high input to
output isolation is achieved. In addition to the TXEN pin, the
AD8324 also incorporates an asynchronous SLEEP pin, which
may be used to further reduce the supply current to approx-
imately 30 μA. Applying Logic 0 to the SLEEP pin places the
amplifier into SLEEP mode. Transitioning into or out of SLEEP
mode may result in a transient voltage at the output of the
amplifier.
In addition to the sleep and transmit disable functions, the
AD8324 provides yet another means of reducing system power
consumption. While in the transmit enable state, the AD8324
incorporates supply current scaling, which allows for lower
power consumption at lower gain codes. Figure 20 shows the
typical relationship between supply current and gain code.
DISTORTION, ADJACENT CHANNEL POWER, AND
DOCSIS
To deliver the DOCSIS required 58 dBmV of QPSK signal and
55 dBmV of 16 QAM signal, the PA is required to deliver up to
61 dBmV. This added power is required to compensate for
losses associated with the diplex filter or other passive compo-
nents that may be included in the upstream path of cable
modems or set-top boxes. It should be noted that the AD8324
was characterized with a differential input signal. Figures 7 to 10
show the AD8324 second and third harmonic distortion perfor-
mance versus the fundamental frequency for various output
power levels. These figures are useful for determining the in-
band harmonic levels from 5 MHz to 65 MHz. Harmonics
higher in frequency (above 42 MHz for DOCSIS and above
65 MHz for Euro-DOCSIS) will be sharply attenuated by the
low-pass filter function of the diplexer.
Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1
states, “Spurious emissions from a transmitted carrier may
occur in an adjacent channel that could be occupied by a carrier
of the same or different symbol rates.” Figure 13 shows the
typical ACP for a 61 dBmV (approximately 12 dBm) QPSK
signal taken at the output of the AD8324 evaluation board. The
transmit channel width and adjacent channel width in Figure 13
correspond to the symbol rates of 160 kSym/s. Table 6 shows
the ACP results for the AD8324 driving a QPSK, 61 dBmV
signal for all conditions in DOCSIS Table 6-9, Adjacent Channel
Spurious Emissions.
UTILIZING DIPLEX FILTERS
The AD8324 was designed to drive 61 dBmV without any
external filtering and still meet DOCSIS spurious emissions and
distortion requirements. However, in most upstream CATV
applications, a diplex filter is used to separate the upstream and
downstream signal paths from one another. The diplex filter
does have insertion loss that the upstream driver needs to over-
come, but it also provides a low-pass filter. The addition of this
low-pass filter to the signal chain can greatly attenuate second
harmonic products of channels above 21 MHz and third
harmonic products of channels at or above 14 MHz up for
diplexers with a 42 MHz upstream cutoff. Similar performance
gains can be achieved using European-specified diplexers to
filter second harmonics for channels above 33 MHz and third
harmonics for channels above 22 MHz (65 MHz upstream
cutoff). This filtering allows the AD8324 to drive up to
63 dBmV of QPSK (this level can vary by application and
modulation type).
NOISE AND DOCSIS
At minimum gain, the AD8324 output noise spectral density is
1.3 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious
Emissions in 5 MHz to 42 MHz, specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 kSym/s is
20 × log [√(1.3
nV
/√
Hz
)
2
× 160
kHz
] + 60 = –65.7
dBmV
Comparing the computed noise power of –65.7 dBmV to the
+8 dBmV signal yields –73.7 dBc, which meets the required
level set forth in DOCSIS Table 6-10. As the AD8324 gain is
increased above this minimum value, the output signal
increases at a faster rate than the noise, resulting in a signal-to-
noise ratio that improves with gain. In transmit disable mode,
the output noise spectral density is 1.1 nV/√Hz, which results in
–67 dBmV when computed over 160 kSym/s. The noise power
was measured directly at the AD8324AR-EVAL’s output.
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| AD8324ACPZ | 功能描述:IC LINE DRIVER CATV 3.3V 20LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| AD8324ACPZ-REEL7 | 功能描述:IC LINE DRIVER CATV 3.3V 20LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8324JRQ | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin QSOP Tube 制造商:Rochester Electronics LLC 功能描述:LOW COST 3.3V CABLE LINE DRIVER - Bulk 制造商:Analog Devices 功能描述:CABLE LINE DRIVER 3.3V SMD 8324 |
| AD8324JRQ-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.3 V Upstream Cable Line Driver |
| AD8324JRQ-REEL | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin QSOP T/R 制造商:Analog Devices 功能描述:SP AMP LINE DRVR AMP SGL 3.47V 20QSOP - Tape and Reel |
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