參數(shù)資料
型號(hào)： AD8137_05
廠商： Analog Devices, Inc.
英文描述： Low Cost, Low Power 12-Bit Differential ADC Driver
中文描述： 低成本，低功耗12位差分ADC驅(qū)動(dòng)器
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 597K
代理商： AD8137_05
AD8137
Estimating DC Errors
Primary differential output offset errors in the AD8137 are due
to three major components: the input offset voltage, the offset
between the V
AN
and V
AP
input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
Rev. B | Page 21 of 24
The first output error component is calculated as
+
R
=
G
G
F
IO
R
R
V
Vo_e
1
, or equivalently as V
IO
/β
(21)
where
V
IO
is the input offset voltage.
The second error is calculated as
(
)
F
IO
G
F
F
R
G
+
G
G
F
IO
R
I
R
R
R
R
R
R
I
Vo_e
=
+
=
2
(22)
where
I
IO
is defined as the offset between the two input bias
currents.
The third error voltage is calculated as
)
(
3
OCM
V
ICM
V
enr
Vo_e
×
=
(23)
where Δ
enr
is the fractional mismatch between the two
feedback resistors.
The total differential offset error is the sum of these three error
sources.
Additional Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network will still force
the output voltages to remain balanced, even when the R
F
/R
G
feedback networks are mismatched. The mismatch, however,
will cause a gain error proportional to the feedback network
mismatch.
Ratio-matching errors in the external resistors will degrade the
ability to reject common-mode signals at the V
AN
and V
IN
input
terminals, similar to a four-resistor difference amplifier made
from a conventional op amp. Ratio-matching errors will also
produce a differential output component that is equal to the
V
OCM
input voltage times the difference between the feedback
factors (βs). In most applications using 1% resistors, this
component amounts to a differential dc offset at the output that
is small enough to be ignored.
Driving a Capacitive Load
A purely capacitive load will react with the bondwire and pin
inductance of the AD8137, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance. The resistor and load
capacitance will form a first-order, low-pass filter, so the resistor
value should be as small as possible. In some cases, the ADCs
require small series resistors to be added on their inputs.
Figure 39 and Figure 42 illustrate transient response vs. capaci-
tive load, and were generated using series resistors in each
output and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered to
when designing with the AD8137. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to the
summing nodes should be removed. Small amounts of stray
summing-node capacitance will cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most high
speed signal applications, and they require at least one line
termination. In analog applications, a matched resistive ter-
mination is generally placed at the load end of the line. This
section deals with how to properly terminate a single-ended
input to the AD8137.
The input resistance presented by the AD8137 input circuitry
is seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and is
simpler, especially considering the fact that standard resistor
values are generally used.
Figure 66 shows the AD8137 in a unity-gain configuration, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 environment.
相關(guān)PDF資料
PDF描述
AD8143 High Speed, Triple Differential Receiver with Comparators
AD8143ACPZ-R2 High Speed, Triple Differential Receiver with Comparators
AD8143ACPZ-REEL High Speed, Triple Differential Receiver with Comparators
AD8143ACPZ-REEL7 High Speed, Triple Differential Receiver with Comparators
AD8145 High Speed, Triple Differential Receiver with Comparators
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD8137ACP 制造商:Analog Devices 功能描述:LOW COST 10-12 BIT DIFFERENTIAL ADC DRIVER - Bulk
AD8137AR 制造商:Analog Devices 功能描述:LOW COST 10-12 BIT DIFFERENTIAL ADC DRIVER - Bulk
AD8137WYCPZ-R7 制造商:AAVID 制造商全稱:AAVID 功能描述:Low Cost, Low Power, Differential ADC Driver
AD8137YCP-EBZ 制造商:Analog Devices 功能描述:AD8137 ADC DRIVER EVALUATION BOARD 制造商:Analog Devices 功能描述:AD8137, ADC DRIVER, EVALUATION BOARD
AD8137YCP-R2 制造商:Analog Devices 功能描述:SP Amp DIFF AMP Single R-R O/P ±6V/12V 8-Pin LFCSP EP T/R
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*