參數(shù)資料
型號: AD8137_05
廠商: Analog Devices, Inc.
英文描述: Low Cost, Low Power 12-Bit Differential ADC Driver
中文描述: 低成本,低功耗12位差分ADC驅(qū)動器
文件頁數(shù): 18/24頁
文件大?。?/td> 597K
代理商: AD8137_05
AD8137
APPLICATIONS
ANALYZING A TYPICAL APPLICATION WITH
MATCHED R
F
AND R
G
NETWORKS
Typical Connection and Definition of Terms
Figure 63 shows a typical connection for the AD8137, using
matched external R
F
/R
G
networks. The differential input
terminals of the AD8137, V
AP
and V
AN
, are used as summing
junctions. An external reference voltage applied to the V
OCM
terminal sets the output common-mode voltage. The two
output terminals, V
OP
and V
ON
, move in opposite directions
in a balanced fashion in response to an input signal.
Rev. B | Page 18 of 24
0
+
V
AP
V
AN
V
ON
V
OP
+
V
O, dm
R
L, dm
AD8137
C
F
R
F
R
G
R
G
C
F
R
F
V
IP
V
OCM
V
IN
Figure 63. Typical Connection
The differential output voltage is defined as
ON
OP
dm
O,
V
V
V
=
(1)
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
2
,
ON
OP
cm
O
V
V
V
+
=
(2)
Output Balance
Output balance is a measure of how well V
OP
and V
ON
are
matched in amplitude and how precisely they are 180° out of
phase with each other. It is the internal common-mode feed-
back loop that forces the signal component of the output
common-mode towards zero, resulting in the near perfectly
balanced differential outputs of identical amplitude and exactly
180° out of phase. The output balance performance does not
require tightly matched external components, nor does it
require that the feedback factors of each loop be equal to each
other. Low frequency output balance is ultimately limited by
the mismatch of an on-chip voltage divider.
Output balance is measured by placing a well-matched resistor
divider across the differential voltage outputs and comparing
the signal at the divider’s midpoint with the magnitude of the
differential output. By this definition, output balance is equal to
the magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differential-
mode voltage:
dm
O
cm
O
V
V
Balance
Output
,
,
=
(3)
The differential negative feedback drives the voltages at the
summing junctions V
AN
and V
AP
to be essentially equal to each
other.
AP
AN
V
V
=
(4)
The common-mode feedback loop drives the output common-
mode voltage, sampled at the midpoint of the two internal
common-mode tap resistors in Figure 61, to equal the voltage
set at the V
OCM
terminal. This ensures that
2
,
dm
O
OCM
V
OP
V
V
+
=
(5)
and
2
,
dm
O
OCM
V
ON
V
V
=
(6)
ESTIMATING NOISE, GAIN, AND BANDWITH WITH
MATCHED FEEDBACK NETWORKS
Estimating Output Noise Voltage and Bandwidth
The total output noise is the root-sum-squared total of several
statistically independent sources. Since the sources are statisti-
cally independent, the contributions of each must be individu-
ally included in the root-sum-square calculation. Table 7 lists
recommended resistor values and estimates of bandwidth and
output differential voltage noise for various closed-loop gains.
For most applications, 1% resistors are sufficient.
Table 7. Recommended Values of Gain-Setting Resistors,
and Voltage Gain for Various Closed-Loop Gains
3 dB
Bandwidth (MHz)
1
1 k
1 k
72
2
1 k
2 k
40
5
1 k
5 k
12
10
1 k
10 k
6
Gain
R
G
()
R
F
()
Total Output
Noise (nV/√Hz)
18.6
28.9
60.1
112.0
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