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參數(shù)資料
| 型號： | AD7739BRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC |
| 中文描述： | 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-153AD, TSSOP-24 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 380K |
| 代理商： | AD7739BRU-REEL7 |
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AD7739
CONTINUOUS CONVERSION MODE
When the mode register is being written, the ADC status byte is
cleared and the RDY pin goes high, regardless of its previous
state. When the continuous conversion command is written to
the mode register, the ADC starts conversion on the channel
selected by the address of the mode register.
Rev. 0 | Page 24 of 32
After the conversion is complete, the relevant channel data
register and channel status register are updated, the relevant
RDY bit in the ADC status register is set, and the AD7739
continues converting on the next enabled channel. The part will
cycle through all enabled channels until put into another mode
or reset. The cycle period will be the sum of all enabled
channels’ conversion times, set by the corresponding channel
conversion time registers.
The RDY bit is reset when the relevant channel data register is
being read. The behavior of the RDY pin depends on the
RDYFN bit in the I/O port register. When the RDYFN bit is 0,
the RDY pin goes low when any channel has unread data. When
the RDYFN bit is set to 1, the RDY pin will go low only if all
enabled channels have unread data.
If an ADC conversion result has not been read before a new
ADC conversion is completed, the new result will overwrite the
previous one. The relevant RDY bit goes low and the RDY pin
goes high for at least 163 MCLK cycles (~26.5 μs), indicating
when the data register is updated, and the previous conversion
data is lost.
If the data register is being read as an ADC conversion
completes, the data register will not be updated with the new
result (to avoid data corruption) and the new conversion
data is lost.
Figure 19 shows the digital interface signal’s sequence for the
continuous conversion mode with Channels 0 and 1 enabled
and the RDYFN bit set to 0. The RDY pin goes low and the data
register is read after each conversion. Figure 20 shows a similar
sequence but with the RDYFN bit set to 1. The RDY pin goes
low and all data registers are read after all conversions are
completed. Figure 21 shows the RDY pin when no data is read
from the AD7739.
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
READ
DATA
CH1
CH1 CONVERSION
CH0 CONVERSION
READ
DATA
CH0
CH1 CONVERSION
READ
DATA
CH0
CH0 CONVERSION
READ
DATA
CH1
03742-0-019
Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
READ
DATA
CH1
CH1 CONVERSION
CH0 CONVERSION
READ
DATA
CH0
CH1 CONVERSION
READ
DATA
CH0
CH0 CONVERSION
READ
DATA
CH1
03742-0-020
Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
03742-0-021
Figure 21. Continuous Conversion, CH0 and CH1, No Data Read
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