參數(shù)資料
型號： AD7739BRU-REEL7
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC
中文描述： 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝： MS-153AD, TSSOP-24
文件頁數(shù)： 10/32頁
文件大?。?/td> 380K
代理商： AD7739BRU-REEL7
AD7739
OUTPUT NOISE AND RESOLUTION SPECIFICATION
The AD7739 can be operated with chopping enabled or
disabled, allowing the ADC to be programmed to optimize
either the offset drift performance or the throughput rate and
channel switching time. Noise tables for these two primary
modes of operation are outlined below for a selection of output
rates and settling times.
Rev. 0 | Page 10 of 32
The AD7739 noise performance depends on the selected
chopping mode, the filter word (FW) value, and the selected
analog input range. The AD7739 noise will not vary
significantly with MCLK frequency.
CHOPPING ENABLED
The first mode, in which the AD7739 is configured with
chopping enabled (CHOP = 1), provides very low noise with
lower output rates.
Table 4 to Table 6 show the –3 dB frequencies and typical
performance versus the channel conversion time and equivalent
output data rate, respectively.
Table 4 shows the typical output rms noise. Table 5 shows the
typical effective resolution based on rms noise. Table 6 shows
the typical output peak-to-peak resolution, representing values
for which there will be no code flicker within a 6-sigma limit.
The peak-to-peak resolutions are not calculated based on rms
noise but on peak-to-peak noise.
These typical numbers are generated from 4096 data samples
acquired in continuous conversion mode with an analog input
voltage set to 0 V and MCLK = 6.144 MHz. The conversion
time is selected via the channel conversion time register.
Table 4. Typical Output RMS Noise in μV vs. Conversion Time and Input Range with Chopping Enabled
FW
Conversion
Time
Register
(μs)
(Hz)
127
0xFF
2689
372
46
0xAE
1001
999
17
0x91
397
2519
10
0x8A
251
3982
9
0x89
230
4342
2
0x82
84
11838
Input Range / RMS Noise (μV)
Conversion
Time
Output Data
Rate
–3 dB
Frequency
(Hz)
200
500
1325
2209
2450
9500
±2.5 V, +2.5 V
±1.25 V, +1.25 V, ±0.625 V, +0.625 V
1.8
2.7
4.8
9.3
10.8
600
1.1
1.7
2.7
4.7
6.3
460
Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled
FW
Conversion
Time
Register
(μs)
(Hz)
127
0xFF
2689
372
46
0xAE
1001
999
17
0x91
397
2519
10
0x8A
251
3982
9
0x89
230
4342
2
0x82
84
11838
Input Range / Effective Resolution (Bits)
Conversion
Time
Output Data
Rate
–3 dB
Frequency
(Hz)
200
500
1325
2209
2450
9500
±2.5 V
+2.5 V
±1.25 V
+1.25 V ±0.625 V +0.625 V
21.4
20.8
20.0
19.0
18.8
12.9
20.4
19.8
19.0
18.0
17.8
11.9
21.2
20.5
19.8
19.0
18.6
12.4
20.2
19.5
18.8
18.0
17.6
11.4
20.2
19.5
18.8
18.0
17.6
11.4
19.2
18.5
17.8
17.0
16.6
10.4
Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled
FW
Conversion
Time
Register
(μs)
(Hz)
127
0xFF
2689
372
46
0xAE
1001
999
17
0x91
397
2519
10
0x8A
251
3982
9
0x89
230
4342
2
0x82
84
11838
Input Range / Peak-to-Peak Resolution (Bits)
Conversion
Time
Output Data
Rate
–3 dB
Frequency
(Hz)
200
500
1325
2209
2450
9500
±2.5 V
+2.5 V
±1.25 V
+1.25 V ±0.625 V +0.625 V
18.6
17.9
17.1
16.2
16.0
10.7
17.6
16.9
16.1
15.2
15.0
9.7
18.3
17.6
16.9
16.2
15.8
9.7
17.3
16.6
15.9
15.2
14.8
8.7
17.3
16.6
15.9
15.2
14.8
8.7
16.3
15.6
14.9
14.2
13.8
7.7
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