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參數(shù)資料
| 型號(hào)： | AD7739BRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC |
| 中文描述： | 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-153AD, TSSOP-24 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大小： | 380K |
| 代理商： | AD7739BRU-REEL7 |
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AD7739
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 12 of 32
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7739
AIN4
AIN5
AIN6
AIN7
SYNC/P1
SCLK
MCLKIN
MCLKOUT
CS
AINCOM/P0
AV
DD
RESET
AIN3
AIN2
AIN1
AIN0
REFIN(+)
DGND
DV
DD
DIN
DOUT
REFIN(–)
AGND
RDY
03742-0-011
Figure 11. Pin Configuration (24-Lead TSSOP)
DV
DD
SERIAL
INTERFACE
CONTROL
LOGIC
MUX
REFERENCE
DETECT
I/O PORT
CLOCK
GENERATOR
24-BIT
Σ
-
ADC
BUFFER
AD7739
CALIBRATION
CIRCUITRY
AV
DD
SCLK
DIN
DOUT
CS
RDY
RESET
AIN4
AIN5
AIN6
AIN7
AINCOM/P0
AIN0
AIN1
AIN2
AIN3
REFIN(–)
REFIN(+)
SYNC/P1
DGND
DV
DD
MCLKIN
MCLKOUT
AGND
AV
DD
03742-0-012
Figure 12. Block Diagram
Table 10. Pin Function Descriptions
Pin No.
1
Mnemonic
SCLK
Description
Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input
to transfer serial data to or from the AD7739.
Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or
external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins.
Alternatively, MCLKIN can be driven with a CMOS compatible clock and MCLKOUT can be
left unconnected.
Master Clock Signal for the ADC. When the master clock for the device is a crystal/
resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an
external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or
can be switched off to reduce the device power consumption. MCLKOUT can drive one
CMOS load.
Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor.
With this input hardwired low, the AD7739 can operate in its 3-wire interface mode using
SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one
device on the serial bus. It can also be used as an 8-bit frame synchronization signal.
Schmitt Triggered Logic Input. Active low input that resets the control logic, interface
logic, digital filter, analog modulator, and all on-chip registers of the part to power-on
status. Effectively, everything on the part except the clock oscillator is reset when the
RESET pin is exercised.
Analog Positive Supply Voltage, 5 V to AGND Nominal.
Analog Inputs Common Terminal/Digital Output. The function of this pin is determined
by the P0 DIR bit in the I/O port register; the digital value can be written as the P0 bit in
the I/O port register. The digital voltage is referenced to analog supplies. When
configured as an input (P0 DIR bit set to 1), the single-ended analog inputs 0 to 7
(AIN0–AIN7) can be referenced to this pin’s voltage level.
2
MCLKIN
3
MCLKOUT
4
CS
5
RESET
6
7
AV
DD
AINCOM/P0
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