參數(shù)資料
型號(hào)： AD7731BRZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/44頁
文件大小： 0K
描述： IC ADC 24BIT SIGMA-DELTA 24-SOIC
標(biāo)準(zhǔn)包裝： 31
位數(shù)： 24
采樣率（每秒）： 6.4k
數(shù)據(jù)接口： DSP，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 125mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極
產(chǎn)品目錄頁面： 779 (CN2011-ZH PDF)
配用： EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731
AD7731
–38–
REV. 0
The 8XC51 is configured in its Mode 0 serial interface mode.
Its serial interface contains a single data line. As a result, the
DATA OUT and DATA IN pins of the AD7731 should be
connected together. This means that the AD7731 must not be
configured for continuous read operation when interfacing to
the 8XC51. The serial clock on the 8XC51 idles high between
data transfers and, therefore, the POL input of the AD7731
should be hard-wired to a logic high. The 8XC51 outputs the
LSB first in a write operation while the AD7731 expects the
MSB first so the data to be transmitted has to be rearranged
before being written to the output serial register. Similarly, the
AD7731 outputs the MSB first during a read operation while
the 8XC51 expects the LSB first. Therefore, the data read into
the serial buffer needs to be rearranged before the correct data
word from the AD7731 is available in the accumulator.
SYNC
RESET
AD7731
POL
DATA OUT
DATA IN
SCLK
CS
P3.0
P3.1
8XC51
DVDD
Figure 19. AD7731 to 8XC51 Interface
AD7731 to ADSP-2103/ADSP-2105 Interface
Figure 20 shows an interface between the AD7731 and the
ADSP-2105 DSP processor. In the interface shown, the
RDY
bit of the Status Register is again monitored to determine when
the Data Register is updated. The alternative scheme is to use
an interrupt driven system, in which case the
RDY output is
connected to the
IRQ2 input of the ADSP-2105. The RFS and
TFS pins of the ADSP-2105 are configured as active low out-
puts and the ADSP-2105 serial clock line, SCLK, is also config-
ured as an output. The POL pin of the AD7731 is hard-wired
low. Because the SCLK from the ADSP-2105 is a continuous
clock, the
CS of the AD7731 must be used to gate off the clock
once the transfer is complete. The
CS for the AD7731 is active
when either the
RFS or TFS outputs from the ADSP-2105 are
active. The serial clock rate on the ADSP-2105 should be lim-
ited to 3 MHz to ensure correct operation with the AD7731.
SYNC
RESET
AD7731
DATA OUT
DATA IN
SCLK
CS
DR
SCLK
ADSP-2105
DVDD
RFS
TFS
DT
POL
Figure 20. AD7731 to ADSP-2105 Interface
REV. A
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