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參數(shù)資料
| 型號： | AD7730LBRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC TRANSDUCER BRIDGE 24SOIC |
| 標準包裝： | 31 |
| 位數(shù)： | 24 |
| 通道數(shù)： | 1 |
| 功率（瓦特）： | 125mW |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 5.25 V |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 產品目錄頁面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7730LEBZ-ND - BOARD EVALUATION FOR AD7730 EVAL-AD7730EBZ-ND - BOARD EVAL FOR AD7730 |
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AD7730/AD7730L
–16–
MD2
MD1
MD0
Operating Mode
0
Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7730 is not
processing any new samples or data. Placing the part in this mode is equivalent to exerting the
SYNC
input pin. However, exerting the
SYNC pin does not actually force these mode bits to 0, 0, 0. The part
returns to this mode after a calibration or after a conversion in Single Conversion Mode. This is the
default condition of these bits after Power-On/Reset.
0
1
Continuous Conversion Mode. In this mode, the AD7730 is continuously processing data and providing
conversion results to the Data Register at the programmed output update rate (as determined by the
Filter Register). For most applications, this would be the normal operating mode of the AD7730.
0
1
0
Single Conversion Mode. In this mode, the AD7730 performs a single conversion, updates the Data
Register, returns to the Sync Mode and resets the mode bits to 0, 0, 0. The result of the single conversion
on the AD7730 in this mode will not be provided until the full settling time of the filter has elapsed.
0
1
Power-Down (Standby) Mode. In this mode, the AD7730 goes into its power-down or standby state.
Placing the part in this mode is equivalent to exerting the
STANDBY input pin. However, exerting
STANDBY does not actually force these mode bits to 0, 1, 1.
1
0
Zero-Scale Self-Calibration Mode. This activates zero-scale self-calibration on the channel selected by
CH1 and CH0 of the Mode Register. This zero-scale self-calibration is performed at the selected gain on
internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the part updates the
contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2, MD1 and
MD0 returning to 0, 0, 0. The
RDY output and bit go high when calibration is initiated and return low
when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and ready
for further operations.
1
0
1
Full-Scale Self-Calibration Mode. This activates full-scale self-calibration on the channel selected by
CH1 and CH0 of the Mode Register. This full-scale self-calibration is performed at the selected gain on
an internally-generated full-scale signal. When this full-scale self-calibration is complete, the part updates
the contents of the appropriate Gain Calibration Register and Offset Calibration Register and returns to
Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The
RDY output and bit go high when
calibration is initiated and return low when this full-scale self-calibration is complete to indicate that the
part is back in Sync Mode and ready for further operations.
1
0
Zero-Scale System Calibration Mode. This activates zero scale system calibration on the channel selected
by CH1 and CH0 of the Mode Register. Calibration is performed at the selected gain on the input volt-
age provided at the analog input during this calibration sequence. This input voltage should remain
stable for the duration of the calibration. When this zero-scale system calibration is complete, the part
updates the contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2,
MD1 and MD0 returning to 0, 0, 0. The
RDY output and bit go high when calibration is initiated and
return low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and
ready for further operations.
1
Full-Scale System Calibration Mode. This activates full-scale system calibration on the selected input
channel. Calibration is performed at the selected gain on the input voltage provided at the analog input
during this calibration sequence. This input voltage should remain stable for the duration of the calibra-
tion. When this full-scale system calibration is complete, the part updates the contents of the appropriate
Gain Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0.
The
RDY output and bit go high when calibration is initiated and return low when this full-scale calibra-
tion is complete to indicate that the part is back in Sync Mode and ready for further operations.
REV. B
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| AD7730LBRZ-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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