參數(shù)資料
型號： AD7730LBRZ
廠商： Analog Devices Inc
文件頁數(shù)： 51/53頁
文件大?。?/td> 0K
描述： IC ADC TRANSDUCER BRIDGE 24SOIC
標(biāo)準(zhǔn)包裝： 31
位數(shù)： 24
通道數(shù)： 1
功率（瓦特）： 125mW
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.25 V
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
產(chǎn)品目錄頁面： 779 (CN2011-ZH PDF)
配用： EVAL-AD7730LEBZ-ND - BOARD EVALUATION FOR AD7730
EVAL-AD7730EBZ-ND - BOARD EVAL FOR AD7730
AD7730/AD7730L
–7–
Figure 3. Signal Processing Chain
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
SCLK
Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial
data to or from the AD7730. This serial clock can be a continuous clock with all data transmitted in a con-
tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted
to or from the AD7730 in smaller batches of data.
2
MCLK IN
Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin
can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The AD7730 is specified
with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of
2.4576 MHz.
SCLK
MCLK IN
DGND
DVDD
SYNC
VBIAS
RDY
CS
MCLK OUT
POL
DIN
DOUT
AGND
AVDD
ACX
AIN1(+)
STANDBY
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
8
17
9
16
10
15
11
TOP VIEW
(Not to Scale)
12
13
AD7730
RESET
REF IN(–)
REF IN(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
ACX
PGA +
SIGMA-DELTA
MODULATOR
SINC3 FILTER
CHOP
22-TAP
FIR FILTER
FASTSTEP
FILTER
CHOP
INPUT CHOPPING
THE ANALOG INPUT TO THE PART CAN BE
CHOPPED. IN CHOPPING MODE, WITH
AC EXCITATION DISABLED, THE INPUT
CHOPPING IS INTERNALTO THE DEVICE. IN
CHOPPING MODE, WITH AC EXCITATION
ENABLED, THE CHOPPING IS ASSUMED
TO BE PERFORMED EXTERNAL TO THE PART
AND NO INTERNAL INPUT CHOPPING IS
PERFORMED. THE INPUT CHOPPING CAN
BE DISABLED, IF DESIRED.
SEE PAGE 26
ANALOG
INPUT
DIGITAL
OUTPUT
SINC3 FILTER
THE FIRST STAGE OF THE DIGITAL FILTERING
ON THE PART IS THE SINC3 FILTER. THE
OUTPUT UPDATE RATE AND BANDWIDTH
OF THIS FILTER CAN BE PROGRAMMED. IN
SKIP MODE, THE SINC3 FILTER IS THE
ONLY FILTERING PERFORMED ON THE PART.
SEE PAGE 26
BUFFER
SKIP MODE
IN SKIP MODE, THERE IS NO SECOND
STAGE OF FILTERING ON THE PART. THE
SINC3 FILTER IS THE ONLY FILTERING
PERFORMED ON THE PART.
SEE PAGE 29
SKIP
OUTPUT
SCALING
22-TAP FIR FILTER
IN NORMAL OPERATING MODE, THE
SECOND STAGE OF THE DIGITAL FILTERING
ON THE PART IS A FIXED 22-TAP FIR
FILTER. IN SKIP MODE, THIS FIR FILTER IS
BYPASSED. WHEN FASTSTEP MODE IS
ENABLED AND A STEP INPUT IS
DETECTED, THE SECOND STAGE FILTERING
IS PERFORMED BY THE FILTER
UNTIL THE OUTPUT OF THIS FILTER
HAS FULLY SETTLED.
SEE PAGE 27
OUTPUT SCALING
THE OUTPUT WORD FROM THE DIGITAL
FILTER IS SCALED BY THE CALIBRATION
COEFFICIENTS BEFORE BEING PROVIDED
AS THE CONVERSION RESULT.
SEE PAGE 29
FASTSTEP FILTER
WHEN FASTSTEP MODE IS ENABLED
AND A STEP CHANGE ON THE INPUT
HAS BEEN DETECTED, THE SECOND
STAGE FILTERING IS PERFORMED BY THE
FASTSTEP FILTER UNTIL THE FIR
FILTER HAS FULLY SETTLED.
SEE PAGE 29
OUTPUT CHOPPING
THE OUTPUT OF THE FIRST STAGE
OF FILTERING ON THE PART CAN
BE CHOPPED. IN CHOPPING MODE,
REGARDLESS OF WHETHER AC
EXCITATION IS ENABLED OR DISABLED,
THE OUTPUT CHOPPING IS
PERFORMED. THE CHOPPING CAN
BE DISABLED, IF DESIRED.
SEE PAGE 26
PGA + SIGMA-DELTA MODULATOR
THE PROGRAMMABLE GAIN CAPABILITY
OF THE PART IS INCORPORATED
AROUND THE SIGMA-DELTA MODULATOR.
THE MODULATOR PROVIDES A HIGH-
FREQUENCY 1-BIT DATA STREAM
TO THE DIGITAL FILTER.
SEE PAGE 26
BUFFER
THE INPUT SIGNAL IS BUFFERED
ON-CHIP BEFORE BEING APPLIED TO
THE SAMPLING CAPACITOR OF THE
SIGMA-DELTA MODULATOR. THIS
ISOLATES THE SAMPLING CAPACITOR
CHARGING CURRENTS FROM THE
ANALOG INPUT PINS.
SEE PAGE 24
REV. B
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