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AD7723
Rev. C | Page 8 of 32
t11
t12
t13
t14
CLKIN
FSI
SCO
(CFMT = 0)
FSO
SDO
t8
01186-
006
D15
D0
D1
D2
D14
D0
D1
D2
D3
D15
D14
D1
D2
D0
D3
D13
D3
D15
32 CLKIN CYCLES
16 CLKIN CYCLES
Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See
Table 3 for Control Inputs, TSI = DOE)
Table 3. Serial Interface (MODE1 = 0, MODE2 = 0)
Control Inputs
Serial Mode
Decimation Ratio (SLDR)
Digital Filter Mode (SLP)
SCO Frequency (SCR)
Output Data Rate
SLDR
SLP
SCR
1
32
Low Pass
fCLKIN
fCLKIN/32
1
0
1
32
Band Pass
fCLKIN
fCLKIN/32
1
0
2
32
Low Pass
fCLKIN/2
fCLKIN/32
1
2
32
Band Pass
fCLKIN/2
fCLKIN/32
1
0
1
3
16
Low Pass
fCLKIN
fCLKIN/16
0
1
0
Table 4. Parallel Interface
Control Inputs
Digital Filter Mode
Decimation Ratio
Output Data Rate
MODE1
MODE2
Band Pass
32
fCLKIN/32
0
1
Low Pass
32
fCLKIN/32
1
0
Low Pass
16
fCLKIN/16
1
t16
t15
DOE
SDO
01186-007
Figure 7. Serial Mode Timing for Data Output Enable and Serial Data Output