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參數(shù)資料
| 型號： | AD7723BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SIGMA-DELTA 44MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1.2M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7723CBZ-ND - BOARD EVALUATION FOR AD7723 |
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AD7723
Rev. C | Page 18 of 32
CIRCUIT DESCRIPTION
The AD7723 ADC employs a Σ-Δ conversion technique to
convert the analog input into an equivalent digital word. The
modulator samples the input waveform and outputs an
equivalent digital word at the input clock frequency, fCLKIN.
Due to the high oversampling rate that spreads the quantization
noise from 0 to fCLKIN/2, the noise energy contained in the band
of interest is reduced (Figure 27A). To further reduce the
quantization noise, a high-order modulator is employed to
shape the noise spectrum so that most of the noise energy is
shifted out of the band of interest (Figure 27B).
The digital filter that follows the modulator removes the large
out-of-band quantization noise (Figure 27C) while also
reducing the data rate from fCLKIN at the input of the filter to
fCLKIN/32 or fCLKIN/16 at the output of the filter, depending on the
state on the MODE1/MODE2 pins in parallel interface mode or
the SLDR pin in serial interface mode. The AD7723 output data
rate is a little over twice the signal bandwidth, which guarantees
that there is no loss of data in the signal band.
Digital filtering has certain advantages over analog filtering.
First, since digital filtering occurs after the A/D conversion, it
can remove noise injected during the conversion process.
Analog filtering cannot remove noise injected during
conversion. Second, the digital filter combines low pass-band
ripple with a steep roll-off while also maintaining a linear phase
response.
NOISE SHAPING
QUANTIZATION NOISE
DIGITAL FILTER CUTOFF FREQUENCY
fCLKIN/2
BAND OF INTEREST
A
B
C
01186-027
fCLKIN/2
Figure 27. Sigma-Delta ADC
The AD7723 employs four or five finite impulse response (FIR)
filters in series. Each individual filter’s output data rate is half
that of the filter’s input data rate. When data is fed to the
interface from the output of the fourth filter, the output data
rate is fCLKIN/16 and the resulting oversampling ratio (OSR) of
the converter is 16. Data fed to the interface from the output of
the fifth filter results in an output data rate of fCLKIN/32 and a
corresponding OSR for the converter of 32. When an output
data rate (ODR) of fCLKIN/32 is selected, the digital filter
response can be set to either low-pass or band-pass. The band-
pass response is useful when the input signal is band limited
because the resulting output data rate is half that required to
convert the band when the low-pass operating mode is used. To
illustrate the operation of this mode, consider a band-limited
signal, as shown in Figure 28A. This signal band can be
correctly converted by selecting the (low-pass) ODR = fCLKIN/16
mode, as shown in Figure 28B. Note that the output data rate is a
little over twice the maximum frequency in the frequency band.
Alternatively, the band-pass mode can be selected, as shown in
Figure 28C. The band-pass filter removes unwanted signals
from dc to just below fCLKIN/64. Rather than outputting data at
fCLKIN/16, the output of the band-pass filter is sampled at
fCLKIN/32. This effectively translates the wanted band to a
maximum frequency of a little less than fCLKIN/64, as shown in
Figure 28D. Halving the output data rate reduces the workload
of any following signal processor and also allows a lower serial
clock rate to be used.
BAND LIMITED SIGNAL
0dB
ODR
LOW-PASS FILTER RESPONSE
SAMPLE
IMAGE
LOW-PASS FILTER. OUTPUT DATA RATE = fCLKIN/16
0dB
SAMPLE
IMAGE
BAND-PASS FILTER
RESPONSE
BAND-PASS FILTER
fCLKIN/16
LOW-PASS FILTER. OUTPUT DATA RATE =
fCLKIN/32
ODR
SAMPLE
IMAGE
FREQUENCY
TRANSLATED
INPUT SIGNAL
0dB
A
B
C
D
01186-028
fCLKIN/16
Figure 28. Band-Pass Operation
The frequency response of the three digital filter operating
modes is shown in Figure 29, Figure 30, and Figure 31.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7723BSZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7723BSZ-REEL | 功能描述:IC ADC 16BIT SIGMA-DELTA 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7723BSZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7724 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual CMOS Modulators |
| AD7724ACPZ | 功能描述:IC MOD SIGMA-DELTA DUAL 制造商:analog devices inc. 系列:* 零件狀態(tài):上次購買時(shí)間 標(biāo)準(zhǔn)包裝:1 |
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