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參數(shù)資料
| 型號(hào)： | AD7671ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT CMOS 1MSPS 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極 |
| 配用： | EVAL-AD7671CBZ-ND - BOARD EVALUATION FOR AD7671 |
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AD7671
–16–
75
70
65
60
55
50
45
40
35
1
PSRR
–
dB
FREQUENCY – kHz
10
100
1000
10000
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
In Impulse Mode, the AD7671 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows a
significant power savings when the conversion rate is reduced,
as shown in Figure 10. This feature makes the AD7671 ideal for
very low power battery applications.
This does not take into account the power, if any, dissipated by
the input resistive scaler, which depends on the input voltage
range used and the analog input voltage even in Power-Down
Mode. There is no power dissipated when the 0 V to 2.5 V is used
or when both the analog input voltage is 0 V and a unipolar range,
0 V to 5 V or 0 V to 10 V, is used.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
100000
10000
1000
100
10
1
0.1
1
10
100
1000
10000
100000
1000000
PO
WER
DISSIP
A
TION
–
W
SAMPLING RATE – SPS
WARP/NORMAL
IMPULSE
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7671 is controlled by the signal
CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The
CNVST signal operates independently of CS
and
RD signals.
CNVST
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 11. Basic Conversion Timing
In Impulse Mode, conversions can be automatically initiated. If
CNVST is held LOW when BUSY is LOW, the AD7671 controls
the acquisition phase and then automatically initiates a new conver-
sion. By keeping
CNVST LOW, the AD7671 keeps the conversion
process running by itself. It should be noted that the analog input
has to be settled when BUSY goes LOW. Also, at power-up,
CNVST should be brought LOW once to initiate the conversion
process. In this mode, the AD7671 could sometimes run slightly
faster than the guaranteed limits in the Impulse Mode of
666 kSPS. This feature does not exist in Warp or Normal Modes.
Although
CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum over-
shoot and undershoot or ringing. It is a good thing to shield the
CNVST trace with ground and also to add a low value serial
resistor (i.e., 50
W) termination close to the output of the
component that drives this line.
For applications where the SNR is critical, the
CNVST signal
should have a very low jitter. To achieve this, some use a dedicated
oscillator for
CNVST generation, or at least to clock it with a
high frequency low jitter clock as shown in Figure 5.
t9
t8
RESET
DATA BUS
BUSY
CNVST
Figure 12. RESET Timing
REV. C
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