- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10093 > AD7671ASTZRL (Analog Devices Inc)IC ADC 16BIT CMOS 1MSPS 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD7671ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT CMOS 1MSPS 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極 |
| 配用： | EVAL-AD7671CBZ-ND - BOARD EVALUATION FOR AD7671 |
AD7671
–18–
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t28
t29
t14
t18
t19
t20
t21
t24
t26
t27
t23
t22
t16
t15
12
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t25
t30
Figure 17. Master Serial Data Timing for Reading (Read after Convert)
EXT/
INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t3
t1
t17
t14
t19
t20 t21
t24
t26
t25
t27
t23
t22
t16
t15
D15
D14
D2
D1
D0
X
12
3
14
15
16
t18
BUSY
SYNC
SCLK
SDOUT
CS, RD
CNVST
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
MASTER SERIAL INTERFACE
Internal Clock
The AD7671 is configured to generate and provide the serial data
clock SCLK when the EXT/
INT pin is held LOW. It also gener-
ates a SYNC signal to indicate to the host when the serial data is
valid. The serial clock SCLK and the SYNC signal can be inverted
if desired. Depending on RDC/SDIN input, the data can be read
after each conversion or during conversion. Figures 17 and 18
show the detailed timing diagrams of these two modes.
Usually, because the AD7671 is used with a fast throughput, the
mode master, read during conversion, is the most recommended
Serial Mode when it can be used.
In Read-during-Conversion Mode, the serial clock and data toggle
at appropriate instants, which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
While the AD7671 is performing a bit decision, it is important that
voltage transients not occur on digital input/output pins or degra-
dation of the conversion result could occur. This is particularly
important during the second half of the conversion phase because
REV. C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-2NB-MX-F4 | CONVERTER MOD DC/DC 95V 75W |
| MS27505E17F35SD | CONN RCPT 55POS BOX MNT W/SCKT |
| VE-2NB-MX-F3 | CONVERTER MOD DC/DC 95V 75W |
| LT1135ACSW#TR | IC TXRX 5V RS232 LP CAPS 20SOIC |
| VI-2T0-MY | CONVERTER MOD DC/DC 5V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7672 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
| AD7672BE03 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
| AD7672BQ03 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
| AD7672BQ03/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| AD7672BQ05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。