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參數(shù)資料
| 型號(hào)： | AD7671ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT CMOS 1MSPS 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極 |
| 配用： | EVAL-AD7671CBZ-ND - BOARD EVALUATION FOR AD7671 |
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AD7671
–12–
Modes of Operation
The AD7671 features three modes of operation, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp Mode allows the fastest conversion rate up to 1 MSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1 ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7671 ideal
for applications where both high accuracy and fast sample rate
are required.
The Normal Mode is the fastest mode (800 kSPS) without any limi-
tation about the time between conversions. This mode makes the
AD7671 ideal for asynchronous applications such as data acquisi-
tion systems, where both high accuracy and fast sample rate are
required.
The Impulse Mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput in
this mode is 666 kSPS. When operating at 100 SPS, for example,
it typically consumes only 15
mW. This feature makes the AD7671
ideal for battery-powered applications.
Transfer Functions
Using the OB/
2C digital input, the AD7671 offers two output
codings: straight binary and twos complement. The ideal transfer
characteristic for the AD7671 is shown in Figure 4 and Table III.
000...000
000...001
000...010
111...101
111...110
111...111
ADC
CODE
–
Straight
Binar
y
ANALOG INPUT
+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
Figure 4. ADC Ideal Transfer Function
CONVERTER OPERATION
The AD7671 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The input analog signal is
first scaled down and level shifted by the internal input resistive
scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V,
and 0 V to 10 V) and bipolar ranges (
±2.5 V, ±5 V, and ±10 V).
The output voltage range of the resistive scaler is always 0 V to
2.5 V. The capacitive DAC consists of an array of 16 binary
weighted capacitors and an additional “LSB” capacitor. The
comparator’s negative input is connected to a “dummy” capacitor
of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND via
SWA. All independent switches are connected to the output of the
resistive scaler. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal. Similarly, the dummy
capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete and the
CNVST input goes
or is LOW, a conversion phase is initiated. When the conversion
phase begins, SWA and SWB are opened first. The capacitor array
and the dummy capacitor are then disconnected from the inputs and
connected to the REFGND input. Therefore, the differential
voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 . . .VREF/65,536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the completion
of this process, the control logic generates the ADC output code
and brings BUSY output LOW.
SWA
COMP
SWB
IND
4R
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C
4C
2C
C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
INC
4R
INA
R
INB
2R
CNVST
65,536C
Figure 3. ADC Simplified Schematic
REV. C
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