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參數(shù)資料
| 型號： | AD7452BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DIF 555KSPS SOT23-8 |
| 標準包裝： | 3,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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AD7452
Rev. B | Page 21 of 28
POWER-UP TIME
The power-up time of the AD7452 is typically 1 s, which
means that with any SCLK frequency up to 10 MHz, one
dummy cycle is always sufficient to allow the device to power
up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal will be acquired properly. The
quiet time, tQUIET, must still be allowed from the point at which
the bus goes back into three-state after the dummy conversion
to the next falling edge of CS.
When running at the maximum throughput rate of 555 kSPS,
the AD7452 powers up and acquires a signal within ±0.5 LSB in
one dummy cycle. When powering up from the power-down
mode with a dummy cycle, as in Figure 38, the track-and-hold,
which was in hold mode while the part was powered down,
returns to track mode after the first SCLK edge the part receives
after the falling edge of CS. This is shown as Point A in
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire VIN, it does not necessarily
mean that a full dummy cycle of 16 SCLKs must always elapse
to power up the device and acquire VIN fully; 1 s is sufficient to
power up the device and acquire the input signal.
For example, if a 5 MHz SCLK frequency is applied to the ADC,
the cycle time is 3.2 s (i.e., 1/(5 MHz) × 16). In one dummy
cycle, 3.2 s, the part is powered up and VIN fully acquired.
However, after 1 s with a 5 MHz SCLK, only five SCLK cycles
would have elapsed. At this stage, the ADC is fully powered up
and the signal acquired. So in this case, CS can be brought high
after the 10th SCLK falling edge and brought low again after a
time, tQUIET, to initiate the conversion.
When power supplies are first applied to the AD7452, the ADC
may power up either in power-down mode or in normal mode.
Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the user wants the part to power up in
power-down mode, the dummy cycle may be used to ensure the
device is in power-down by executing a cycle such as the one
shown in Figure 37.
Once supplies are applied to the AD7452, the power-up time is
the same as that when powering up from power-down mode. It
takes approximately 1 s to power up fully if the part powers up
in normal mode. It is not necessary to wait 1 s before executing
a dummy cycle to ensure the desired mode of operation.
Instead, the dummy cycle can occur directly after power is
supplied to the ADC. If the first valid conversion is performed
directly after the dummy conversion, care must be taken to
ensure that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-down
mode, the part returns to track mode upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
powers up initially after supplies are applied, the track-and-hold
is already in track mode. This means if (assuming one has the
facility to monitor the ADC supply current) the ADC powers up
in the desired mode of operation, and thus a dummy cycle is
not required to change the mode, and a dummy cycle is not
required to place the track-and-hold into track mode.
CS
SCLK
SDATA
1
10
16
1
10
16
A
THIS PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
PART BEGINS
TO POWER UP
INVALID DATA
VALID DATA
tPOWER-UP
03154-A
-038
Figure 38. Exiting Power-Down Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7453 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential, 555 kSPS, 12-Bit ADC in an 8-Lead SOT-23 |
| AD7453ART-REEL7 | 制造商:Analog Devices 功能描述: |
| AD7453ARTZ-REEL7 | 功能描述:IC ADC 12BIT DFF 600KSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應商設備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7453BRT-R2 | 制造商:Analog Devices 功能描述:ADC Single SAR 555ksps 12-bit Serial 8-Pin SOT-23 T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT P/DIFF I/PUT, 600KSPS ADC I.C. - Bulk |
| AD7453BRT-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 555ksps 12-bit Serial 8-Pin SOT-23 T/R |
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