參數(shù)資料
型號(hào)： AD7352YRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 0K
描述： IC ADC DUAL 12BIT 3MSPS 16TSSOP
設(shè)計(jì)資源： DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 3M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 45mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
AD7352
Rev. A | Page 16 of 20
FULL POWER-DOWN MODE
Full power-down mode is intended for use in applications
where throughput rates slower than those in partial power-
down mode are required because power-up from a full power-
down takes substantially longer than that from a partial power-
down. This mode is more suited to applications in which a
series of conversions performed at a relatively high throughput
rate are followed by a long period of inactivity and, thus, power-
down. When the AD7352 is in full power-down mode, all
analog circuitry is powered down including the on-chip
reference and reference buffers. Full power-down mode is
entered in a similar way as partial power-down mode, except
that the timing sequence shown in Figure 25 must be executed
twice. The conversion process must be interrupted in a similar
fashion by bringing CS high anywhere after the second falling
edge of SCLK and before the 10th falling edge of SCLK. The
device enters partial power-down mode at this point.
To reach full power-down mode, the next conversion cycle must
be interrupted in the same way, as shown in Figure 27. When
CS is brought high in this window of SCLKs, the part fully
powers down. Note that it is not necessary to complete the 14 or
16 SCLKs once CS has been brought high to enter a power-
down mode.
To exit full power-down mode and power-up the AD7352,
perform a dummy conversion, similar to powering up from
partial power-down. On the falling edge of CS, the device begins to
power up as long as CS is held low until after the falling edge of
the 10th SCLK. The required power-up time must elapse before
a conversion can be initiated, as shown in
.
SCLK
CS
SDATAA
SDATAB
INVALID DATA
VALID DATA
110
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP;
SEE THE POWER-UP TIMES SECTION.
tPOWER-UP1
07
04
4
-02
0
Figure 26. Exiting Partial Power-Down Mode
THREE-STATE
110
14
2
SCLK
CS
SDATAA
SDATAB
THREE-STATE
110
2
INVALID DATA
THE PART BEGINS
TO POWER UP.
THE PART ENTERS
PARTIAL POWER-DOWN MODE.
THE PART ENTERS
FULL POWER-DOWN MODE.
14
070
44
-02
1
Figure 27. Entering Full Power-Down Mode
SCLK
SDATAA
SDATAB
INVALID DATA
VALID DATA
1
10
14
1
THE PART BEGINS
TO POWER UP.
tPOWER-UP2
CS
07
04
4-
0
22
THE PART IS FULLY POWERED UP;
SEE THE POWER-UP TIMES SECTION.
Figure 28. Exiting Full Power-Down Mode
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AD7356_08 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC
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