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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7228ABP |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 6/8闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 8BIT OCTAL W/AMP 28-PLCC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Product Discontinuance 27/Oct/2011 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 瑷�(sh猫)缃檪闁擄細 | 5µs |
| 浣嶆暩(sh霉)锛� | 8 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 8 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 310mW |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-PLCC锛�11.51x11.51锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 8 闆诲锛屽柈妤�锛�8 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 200k |
AD7228A
REV. A
鈥�6鈥�
Table II. Unipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
+V
REF
255
256
1 0 0 0
0 0 0 1
+V
REF
129
256
1 0 0 0
0 0 0 0
+V
REF
128
256
=+
V
REF
2
0 1 1 1
1 1 1 1
+V
REF
127
256
0 0 0 0
0 0 0 1
+V
REF
1
256
0 0 0 0
0 V
Note: 1 LSB = (VREF)(2
鈥�8) = V
REF
1
256
BIPOLAR OUTPUT OPERATION
Each of the DACs on the AD7228A can be individually config-
ured for bipolar output operation. This is possible using one ex-
ternal amplifier and two resistors per channel. Figure 8 shows a
circuit used to implement offset binary coding (bipolar opera-
tion) with DAC1 of the AD7228A. In this case
V
OUT =
1
+ R2
R1
D
1 V REF
() 鈥� R2
R1
V
REF
()
With R1 = R2
VOUT = (2D1 鈥� 1) (VREF)
where D1 is a fractional representation of the digital word in
latch 1 of the AD7228A. (0
鈮� D
1
鈮� 255/256)
Figure 8. Bipolar Output Circuit
Table III. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
+V
REF
127
128
1 0 0 0
0 0 0 1
+V
REF
1
128
1 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
鈥揤
REF
1
128
0 0 0 0
0 0 0 1
鈥揤
REF
127
128
0 0 0 0
鈥揤
REF
128
= 鈥揤
REF
Mismatch between R1 and R2 causes gain and offset errors, and
therefore, these resistors must match and track over temperature.
Once again, the AD7228A can be operated from single supply
or from dual supplies. Table III shows the digital code versus
output voltage relationship for the circuit of Figure 8 with
R1 = R2.
AC REFERENCE SIGNAL
In some applications it may be desirable to have an ac signal ap-
plied as the reference input to the AD7228A. The AD7228A
has multiplying capability within the upper (+10 V) and lower
(+2 V) limits of reference voltage when operated with dual sup-
plies. Therefore, ac signals need to be ac coupled and biased up
before being applied to the reference input. Figure 9 shows a
sine-wave signal applied to the reference input of the AD7228A.
For input frequencies up to 50 kHz, the output distortion typi-
cally remains less than 0.1%. The typical 3 dB bandwidth for
small signal inputs is 800 kHz.
Figure 9. Applying a AC Signal to the AD7228A
TIMING DESKEW
A common problem in ATE applications is the slowing or
鈥渞ounding-off鈥� of signal edges by the time they reach the
pin-driver circuitry. This problem can easily be overcome by
鈥渟quaring-up鈥� the edge at the pin-driver. However, since each
edge will not have been 鈥渞ounded-off鈥� by the same extent, this
鈥渟quaring-up鈥� could lead to incorrect timing relationship be-
tween signals. This effect is shown in Figure 10a.
Figure 10a. Time Skewing Due to Slowing of Edges
The circuit of Figure 10b shows how two DACs of the
AD7228A can help in overcoming this problem. The same two
signals are applied to this circuit as were applied in Figure 10b.
The output of each DAC is applied to one input of a high-speed
comparator, and the signals are applied to the other inputs.
Varying the output voltage of the DAC effectively varies the
trigger point at which the comparator flips. Thus the timing re-
lationship between the two signals can be programmably cor-
rected (or deskewed) by varying the code to the DAC of the
AD7228A. In a typical application, the code is loaded to the
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| AD7228ABP-REEL | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:DAC 8-CH R-2R 8-bit 28-Pin PLCC T/R |
| AD7228ABPZ | 鍔熻兘鎻忚堪:IC DAC 8BIT OCTAL W/AMP 28-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 瑷�(sh猫)缃檪闁�:4.5µs 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOICN 鍖呰:鍓垏甯� (CT) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:* 鍏跺畠鍚嶇ū:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD7228ABPZ-REEL | 鍔熻兘鎻忚堪:IC DAC 8BIT OCTAL W/AMP 28-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤碉紱1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
| AD7228ABQ | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk |
| AD7228ABR | 鍔熻兘鎻忚堪:IC DAC 8BIT LC2MOS OCTAL 24SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
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