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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7228ABP |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/8闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DAC 8BIT OCTAL W/AMP 28-PLCC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Product Discontinuance 27/Oct/2011 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 瑷�(sh猫)缃檪闁擄細 | 5µs |
| 浣嶆暩(sh霉)锛� | 8 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 8 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 310mW |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-PLCC锛�11.51x11.51锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 8 闆诲锛屽柈妤碉紱8 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 200k |
SWITCHING CHARACTERISTICS
1, 2
Limit at 25
掳C
Limit at TMIN, TMAX
Parameters
All Grades
(B, C Versions)
(T, U Versions)
Units
Conditions/Comments
t1
0
ns min
Address to WR Setup Time
t2
0
ns min
Address to WR Hold Time
t3
70
90
100
ns min
Data Valid to WR Setup Time
t4
10
ns min
Data Valid to WR Hold Time
t5
95
120
150
ns min
Write Pulse Width
NOTES
1Sample tested at 25
掳C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, t
R = tF = 5 ns.
2Timing measurement reference level is
V
INH + V INL
2
INTERFACE LOGIC INFORMATION
Address lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.
Table I. AD7228A Truth Table
AD7228A Control Inputs
AD7228A
WR
A2
A1
A0
Operation
H
X
No Operation
Device Not Selected
LLLL
DAC 1 Transparent
g
L
DAC 1 Latched
LLLH
DAC 2 Transparent
L
H
L
DAC 3 Transparent
L
H
DAC 4 Transparent
L
H
L
DAC 5 Transparent
L
H
L
H
DAC 6 Transparent
L
H
L
DAC 7 Transparent
L
H
DAC 8 Transparent
H = High State
L = Low State
X = Don鈥檛 Care
+5 V SUPPLY OPERATION
BC
T
U
Parameter
Version
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
8888
Bits
Relative Accuracy
卤 2
LSB max
Differential Nonlinearity
卤 1
LSB max
Guaranteed Monotonic
Full-Scale Error
卤 4
卤 2
卤 4
卤 2
LSB max
Zero Code Error
@ 25
掳C
卤 30
卤 20
卤 30
卤 20
mV max
TMIN to TMAX
卤 40
卤 30
卤 40
卤 30
mV max
REFERENCE INPUT
Reference Input Range
1.2
V min
1.3
V max
Reference Input Resistance
2222k
min
Reference Input Capacitance
500
pF max
POWER REQUIREMENTS
Positive Supply Range
4.75/5.25
V min/V max
For Specified Performance
Positive Supply Current
@ 25
掳C
16161616
A max
TMIN to TMAX
20
22
A max
Negative Supply Current
@ 25
掳C
14141414
A max
TMIN to TMAX
18
20
A max
NOTES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when VSS = 0 V.
Specifications subject to change without notice.
(VDD = +5 V
5%, VSS; = 0 to 鈥�5 V
10%, GND = 0 V, VREF = +1.25 V, RL = 2 k , CL = 100 pF
unless otherwise noted.) AII specifications TMIN to TMAX unless otherwise noted.
(See Figures 1, 2; VDD = +5 V
5% or +10.8 V to +16.5 V; VSS = 0 V or 鈥�5 V
10%)
Figure 1. Input Control Logic
Figure 2. Write Cycle Timing Diagram
AD7228A
REV. A
鈥�3鈥�
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