- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗10801 > AD7228ABP (Analog Devices Inc)IC DAC 8BIT OCTAL W/AMP 28-PLCC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7228ABP |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/8闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 8BIT OCTAL W/AMP 28-PLCC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Product Discontinuance 27/Oct/2011 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 瑷�(sh猫)缃檪闁擄細 | 5µs |
| 浣嶆暩(sh霉)锛� | 8 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 8 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 310mW |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-PLCC锛�11.51x11.51锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 8 闆诲锛屽柈妤�锛�8 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 200k |
AD7228A
REV. A
鈥�4鈥�
ABSOLUTE MAXIMUM RATINGS
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥�0.3 V, +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥�0.3 V, +24 V
Digital Input Voltage to GND . . . . . . . . . . . . . . . 鈥�0.3 V, VDD
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥�0.3V, VDD
VOUT to GND
2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS, VDD
Power Dissipation (Any Package) to +75
掳C . . . . . . . 1000 mW
Derates above 75
掳C by . . . . . . . . . . . . . . . . . . . . 2.0 mW/掳C
Operating Temperature
Commercial . . . . . . . . . . . . . . . . . . . . . . . . 鈥�40
掳C to +85掳C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥�40
掳C to +85掳C
Extended . . . . . . . . . . . . . . . . . . . . . . . . . 鈥�55
掳C to +125掳C
Storage Temperature . . . . . . . . . . . . . . . . . . 鈥�65
掳C to +150掳C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300
掳C
NOTES
1Stresses above those listed under 鈥淎bsolute Maximum Ratings鈥� may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Outputs may be shorted to any voltage in the range V
SS to VDD provided that the
power dissipation of the package is not exceeded. Typical short circuit current for
a short to GND or VSS is 50 mA.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7228A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP AND SOIC
PLCC
ORDERING GUIDE
Total
Temperature
Unadjusted
Package
Model1
Range
Error (LSB)
Option2
AD7228ABN
鈥�40
掳C to +85掳C
卤2 max
N-24
AD7228ACN
鈥�40
掳C to +85掳C
卤1 max
N-24
AD7228ABP
鈥�40
掳C to +85掳C
卤2 max
P-28A
AD7228ACP
鈥�40
掳C to +85掳C
卤1 max
P-28A
AD7228ABR
鈥�40
掳C to +85掳C
卤2 max
R-24
AD7228ACR
鈥�40
掳C to +85掳C
卤1 max
R-24
AD7228ABQ
鈥�40
掳C to +85掳C
卤2 max
Q-24
AD7228ACQ
鈥�40
掳C to +85掳C
卤1 max
Q-24
AD7228ATQ
3
鈥�55
掳C to +125掳C
卤2 max
Q-24
AD7228AUQ
3
鈥�55
掳C to +125掳C
卤1 max
Q-24
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet and availability.
2N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
R = Small Outline IC (SOIC).
3These grades will be available to /883B processing only.
CIRCUIT INFORMATION
D/A SECTION
The AD7228A contains eight identical, 8-bit, voltage-mode
digital-to-analog converters. The output voltages from the con-
verters have the same polarity as the reference voltage, allowing
single supply operation. A novel DAC switch pair arrangement
on the AD7228A allows a reference voltage range from +2 V to
+10 V when operated from a VDD of +15 V. Each DAC consists
of a highly stable, thin-film, R-2R ladder and eight high-speed
NMOS switches. The simplified circuit diagram for one channel
is shown in Figure 3. Note that VREF and GND are common to
all eight DACs.
Figure 3. D/A Simplified Circuit Diagram
The input impedance at the VREF pin of the AD7228A is the
parallel combination of the eight individual DAC reference in-
put impedances. It is code dependent and can vary from 2 k
to
infinity. The lowest input impedance occurs when all eight
DACs are loaded with digital code 01010101. Therefore, it is
important that the external reference source presents a low out-
put impedance to the VREF terminal of the AD7228A under
changing load conditions. Due to transient currents at the refer-
ence input during digital code changes a 0.1
F (or greater)
decoupling capacitor is recommended on the VREF input for dc
applications. The nodal capacitance at the reference terminal is
also code dependent and typically varies from 120 pF to
350 pF.
Each VOUT pin can be considered as a digitally programmable
voltage source with an output voltage:
VOUTN = DN VREF
where DN is a fractional representation of the digital input
code and can vary from 0 to 255/256.
The output impedance is that of the output buffer amplifier as
described in the following section.
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|---|---|
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD7228ABP-REEL | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:DAC 8-CH R-2R 8-bit 28-Pin PLCC T/R |
| AD7228ABPZ | 鍔熻兘鎻忚堪:IC DAC 8BIT OCTAL W/AMP 28-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 瑷�(sh猫)缃檪闁�:4.5µs 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOICN 鍖呰:鍓垏甯� (CT) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:* 鍏跺畠鍚嶇ū:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD7228ABPZ-REEL | 鍔熻兘鎻忚堪:IC DAC 8BIT OCTAL W/AMP 28-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
| AD7228ABQ | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk |
| AD7228ABR | 鍔熻兘鎻忚堪:IC DAC 8BIT LC2MOS OCTAL 24SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
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