(VDD = 10.8 V to 16.5 V; VSS <" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD7228ABP
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 2/8闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DAC 8BIT OCTAL W/AMP 28-PLCC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Data Converter Fundamentals
DAC Architectures
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Product Discontinuance 27/Oct/2011
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
瑷�(sh猫)缃檪闁擄細 5µs
浣嶆暩(sh霉)锛� 8
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 骞惰伅(li谩n)
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 8
闆诲闆绘簮锛� 闆� ±
鍔熺巼鑰楁暎锛堟渶澶э級锛� 310mW
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 28-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 28-PLCC锛�11.51x11.51锛�
鍖呰锛� 绠′欢
杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� 8 闆诲锛屽柈妤�锛�8 闆诲锛岄洐妤�
閲囨ǎ鐜囷紙姣忕锛夛細 200k
REV. A
鈥�2鈥�
AD7228A鈥揝PECIFICATIONS
(VDD = 10.8 V to 16.5 V; VSS = 鈥�5 V
10%; GND = 0 V; VREF = +2 V to +10 V
1; R
L = 2 k
, C
L = 100 pF unless otherwise
noted.) All specifications TMIN to TMAX unless otherwise noted.
5Sample tested at 25
掳C to ensure compliance.
6The glitch impulse transferred to the output of one converter (not addressed) due to a
change in the digital input code to another addressed converter.
Specifications subject to change without notice.
(VDD = +15 V
10%, VSS; = GND = 0 V; VREF = +10 V, RL = 2 k
, C
L = 100 pF unless otherwise noted.)
AII specifications TMIN to TMAX unless otherwise noted.
DUAL SUPPLY
BC
T
U
Parameter
Version
2
Version
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
8
Bits
Total Unadjusted Error
3
卤 2
卤 1
卤 2
卤 1
LSB max
VDD = +15 V 卤 10%, VREF = +10 V
Relative Accuracy
卤 1
卤 1/2
卤 1
卤 1/2
LSB max
Differential Nonlinearity
卤 1
LSB max
Guaranteed Monotonic
Full-Scale Error
4
卤 1
卤 1/2
卤 1
卤 1/2
LSB max
Typical tempco is 5 ppm/
掳C with V
REF = +10 V
Zero Code Error
@ 25
掳C
卤 25
卤 15
卤 25
卤 15
mV max
Typical tempco is 30
V/掳C
TMIN to TMAX
卤 30
卤 20
卤 30
卤 20
mV max
Minimum Load Resistance
2
k
min
VOUT = +10 V
REFERENCE INPUT
Voltage Range
1
2 to 10
V min/V max
Input Resistance
2
k
min
Input Capacitance
5
500
pF max
Occurs when each DAC is loaded with all 1s.
AC Feedthrough
鈥�70
鈥�7 0
dB typ
VREF = 8 V p-p Sine Wave @ 10 kHz
DIGITAL INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Leakage Current
卤 1
A max
VIN = 0 V or VDD
Input Capacitance
5
8
pF max
Input Coding
Binary
DYNAMIC PERFORMANCE
5
Voltage Output Slew Rate
2
V/
s min
Voltage Output Settling Time
Positive Full-Scale Change
5
s max
VREF = +10 V; Settling Time to 卤 1/2 LSB
Negative Full-Scale Change
5
s max
VREF = +10 V; Settling Time to 卤 1/2 LSB
Digital Feedthrough
50
nV secs typ
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Digital Crosstalk
6
50
nV secs typ
Code transition all 0s to all 1s. VREF = +10 V; WR = 0 V
POWER SUPPLIES
VDD Range
10.8/16.5
V min/V max
For Specified Performance
VSS Range
鈥�4.5/鈥�5.5
V min/V max
For Specified Performance
IDD
Outputs Unloaded; VIN = VINL or VINH
@ 25
掳C
16
mA max
TMIN to TMAX
20
22
mA max
ISS
Outputs Unloaded; VIN = VINL or VINH
@ 25
掳C
14
mA max
TMIN to TMAX
18
20
mA max
SINGLE SUPPLY
STATIC PERFORMANCE
Resolution
8
Bits
Total Unadjusted Error
3
卤 2
卤 1
卤 2
卤 1
LSB max
Differential Nonlinearity
卤 1
LSB max
Guaranteed Monotonic
Minimum Load Resistance
2
k
min
VOUT = +10 V
REFERENCE INPUT
Input Resistance
2
k
min
Input Capacitance
5
500
pF max
Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
As per Dual Supply Specifications
DYNAMIC PERFORMANCE
5
Voltage Output Slew Rate
2
V/
s min
Voltage Output Settling Time
Positive Full-Scale Change
5
s max
Settling Time to
卤1/2 LSB
Negative Full-Scale Change
7
s max
Settling Time to
卤1/2 LSB
Digital Feedthrough
50
nV secs typ
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Digital Crosstalk
6
50
nV secs typ
Code transition all 0s to all 1s. VREF = +10 V, WR = 0 V
POWER SUPPLIES
VDD Range
13.5/16.5
V min/V max
For Specified Performance
IDD
Outputs Unloaded; VIN = VINL or VINH
@ 25
掳C
16
mA max
TMIN to TMAX
20
22
mA max
NOTES
1V
OUT must be less than VDD by 3.5 V to ensure correct operation.
2Temperature ranges are as follows:
B, C Versions; 鈥�40
掳C to +85掳C
T, U Versions; 鈥�55
掳C to +125掳C
3Total Unadjusted Error includes zero code error, relative accuracy and full-scale error.
4Calculated after zero code error has been adjusted out.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AD7228ABP-REEL 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:DAC 8-CH R-2R 8-bit 28-Pin PLCC T/R
AD7228ABPZ 鍔熻兘鎻忚堪:IC DAC 8BIT OCTAL W/AMP 28-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 瑷�(sh猫)缃檪闁�:4.5µs 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOICN 鍖呰:鍓垏甯� (CT) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤碉紱1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:* 鍏跺畠鍚嶇ū:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD7228ABPZ-REEL 鍔熻兘鎻忚堪:IC DAC 8BIT OCTAL W/AMP 28-PLCC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k
AD7228ABQ 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk
AD7228ABR 鍔熻兘鎻忚堪:IC DAC 8BIT LC2MOS OCTAL 24SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤碉紱1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k
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